hi_board.h

华为 HI3510 BOOTLOADER HIBOOT 源码包

#endif








#if defined(BOARD_HI3560FPGA)||defined(BOARD_HI3560DEMO)

	#define DDRC_CONTROL	(DDRC_BASE)
	#define DDRC_STATUS	(DDRC_BASE + 0x4)
	#define DDRC_CONFIG	(DDRC_BASE + 0x8)
	#define DDRC_DYNAMIC_CONTROL	(DDRC_BASE + 0x020)

	/* Here x=0..3 .*/
	#define DDRC_DYNAMIC_CONFIG(x)       (DDRC_BASE + 0x100 + x * 0x20)
	#define DDRC_DYNAMIC_RASCAS(x)       (DDRC_BASE + 0x100 + x * 0x20 + 0x4)

	#define DDRC_DYNAMIC_REFRESH         (DDRC_BASE + 0x024)
	#define DDRC_DYNAMIC_READCONFIG      (DDRC_BASE + 0x028)
	#define DDRC_DYNAMIC_TRP             (DDRC_BASE + 0x030)
	#define DDRC_DYNAMIC_TRAS            (DDRC_BASE + 0x034)
	#define DDRC_DYNAMIC_TSREX           (DDRC_BASE + 0x038)
	#define DDRC_DYNAMIC_TWR             (DDRC_BASE + 0x044)
	#define DDRC_DYNAMIC_TRC             (DDRC_BASE + 0x048)
	#define DDRC_DYNAMIC_TRFC            (DDRC_BASE + 0x04C)
	#define DDRC_DYNAMIC_TXSR            (DDRC_BASE + 0x050)
	#define DDRC_DYNAMIC_TRRD            (DDRC_BASE + 0x054)
	#define DDRC_DYNAMIC_TMRD            (DDRC_BASE + 0x058)
	#define DDRC_DYNAMIC_TCDLR           (DDRC_BASE + 0x05C)


	#define DDREModeRegAddr  (DDR_BASE + 0x484000)
	#define DDRModeRegAddr1  (DDR_BASE + 0x001000) 
	#define DDRModeRegAddr2  (DDR_BASE + 0x084000)
	
	/* Here x=0..4 .*/
	#define DDRC_AHB_CONTROL(x)          (DDRC_BASE + 0x400 + x * 0x20)
	
	
	
	
	/* SSMC register description :*/
	#define SMBIDCYR(x)            (SSMC_BASE + x * 0x20)
	#define SMBWSTRDR(x)           (SSMC_BASE + x * 0x20 + 0x04)
	#define SMBWSTWRR(x)           (SSMC_BASE + x * 0x20 + 0x08)
	#define SMBWSTOENR(x)          (SSMC_BASE + x * 0x20 + 0x0C)
	#define SMBWSTWENR(x)          (SSMC_BASE + x * 0x20 + 0x10)
	#define SMBCR(x)               (SSMC_BASE + x * 0x20 + 0x14)
	#define SMBSR(x)               (SSMC_BASE + x * 0x20 + 0x18)
	#define SMBWSTBRDR(x)          (SSMC_BASE + x * 0x20 + 0x1C)

	#define SSMCSR                 (SSMC_BASE + 0x200)
	#define SSMCCR                 (SSMC_BASE + 0x204)
	
	
	#define FLASH_TYPE_J3
	
	#define FLASH_BLOCK_SIZE            0x00020000   /* 128Kbytes per bank */
	#define FLASH_PARTS_PER_BANK        1
	
	
#endif	
	
	
	
#if defined(BOARD_HI3517FPGA)||defined(BOARD_HI3517DEMO)
	
	#define FLASH_TYPE_L18
	/* #define FLASH_TYPE_J3  */
	
	#ifdef FLASH_TYPE_L18
		#define FLASH_PARAM_BOTTOM
		/*define FLASH_PARAM_TOP */
		#define FLASH_PARAM_BLOCK_SIZE      0x00008000   /* 32Kbytes per param bank, in fact there's 2banks. */
		#define FLASH_PARAM_BLOCK_NUM       4
	#endif

	#define FLASH_BLOCK_SIZE            0x00020000   /* 128Kbytes per bank, in fact there's 2banks. */
	#define FLASH_PARTS_PER_BANK        2
#endif

/*
	** VIC register address,revised by yuanyabin 2004-04-28 ***
*/

/* Modified according to the PXP by yuanyabin */

#define VIC_IRQ_STATUS       	 (ECS_VIC_BASE + 0x000)
#define VIC_FIQ_STATUS       	 (ECS_VIC_BASE + 0x004)

#define VIC_RAW_INT  	         (ECS_VIC_BASE + 0x008)
#define VIC_INT_SELECT       	 (ECS_VIC_BASE + 0x00C)
#define VIC_INT_ENABLE           (ECS_VIC_BASE + 0x010)
#define VIC_INT_ENABLE_MASK      0xFFFFFFFF

#define VIC_INT_ENABLE_CLR   	 (ECS_VIC_BASE + 0x014)
#define VIC_SOFT_INT         	 (ECS_VIC_BASE + 0x018)
#define VIC_SOFT_INT_CLR         (ECS_VIC_BASE + 0x01C)

#define VIC_PROTECTION_ENABLE    (ECS_VIC_BASE + 0x020)

#define VIC_VECT_ADDR            (ECS_VIC_BASE + 0x030)
#define VIC_DEF_VECT_ADDR        (ECS_VIC_BASE + 0x034)

#define VIC_VECT_ADDRX(addr_num) (ECS_VIC_BASE + 0x100 + addr_num * 4)

#define VIC_VECT_CNTLX(addr_num) (ECS_VIC_BASE + 0x200 + addr_num * 4)







/*
	** UART register and freq description.**
*/ 
/****commented by yuanyabin 2004-04-28.********************/
/**********************************************************/

/* UART Frequency definition. */
#define AMBA_UART_FREQ      HCLK_FREQ    /* UARTs Freqency is 24MHz or HCLK_FREQ. */
#define AMBA_UART_FREQ_MHZ  (AMBA_UART_FREQ/1000000)

/* General register adress definitions */
#define UART_RFR        0x000    /* Receive Fifo reg.    */
#define UART_TFR        0x000    /* Transmit Fifo reg.   */

#define UART_RSR        0x004    /* receive status register   */
#define UART_ECR        0x004    /* error clear reg*/
#define UART_FR         0x018    /*flag register*/
#define UART_ILPR       0x020    /*IrDA low power register*/
#define UART_IBRD       0x024    /*Integer baud rate dividor*/
#define UART_FBRD       0x028    /*fractional baud rate dividor*/
#define UART_LCR        0x02c    /* line control reg */

#define UART_CR         0x030    /* control reg */
#define UART_IFLS       0x034    /*interrupt level select register*/
#define UART_IMSC       0x038    /*interrupt mask set clear register*/
#define UART_RIS        0x03c    /*raw interrupt status register*/
#define UART_MIS        0x040    /*masked interrupt status register*/
#define UART_ICR        0x044    /*interrupt clear register*/
#define UART_DMACR      0x048    /*DMA control register*/


/* UART0 register definitions */
#define UART0_RFR        (UART0_BASE + UART_RFR)    /* Receive Fifo reg.    */
#define UART0_TFR        (UART0_BASE + UART_TFR)    /* Transmit Fifo reg.   */

#define UART0_RSR        (UART0_BASE + UART_RSR)    /* Receive status register   */
#define UART0_ECR        (UART0_BASE + UART_ECR)    /* Error clear reg*/
#define UART0_FR         (UART0_BASE + UART_FR)     /* Flag register*/
#define UART0_ILPR       (UART0_BASE + UART_ILPR)   /* IrDA low power register*/
#define UART0_IBRD       (UART0_BASE + UART_IBRD)   /* Integer baud rate dividor*/
#define UART0_FBRD       (UART0_BASE + UART_FBRD)   /* Fractional baud rate dividor*/
#define UART0_LCR        (UART0_BASE + UART_LCR)    /* Line control reg */

#define UART0_CR         (UART0_BASE + UART_CR)     /* Control reg */
#define UART0_IFLS       (UART0_BASE + UART_IFLS)   /* Interrupt level select register*/
#define UART0_IMSC       (UART0_BASE + UART_IMSC)   /* Interrupt mask set clear register*/
#define UART0_RIS        (UART0_BASE + UART_RIS)    /* Raw interrupt status register*/
#define UART0_MIS        (UART0_BASE + UART_MIS)    /* Masked interrupt status register*/
#define UART0_ICR        (UART0_BASE + UART_ICR)    /* Interrupt clear register*/
#define UART0_DMACR      (UART0_BASE + UART_DMACR)  /* DMA control register*/


/* UART1 register definitions */
#define UART1_RFR        (UART1_BASE + UART_RFR)    /* Receive Fifo reg.    */
#define UART1_TFR        (UART1_BASE + UART_TFR)    /* Transmit Fifo reg.   */

#define UART1_RSR        (UART1_BASE + UART_RSR)    /* Receive status register   */
#define UART1_ECR        (UART1_BASE + UART_ECR)    /* Error clear reg*/
#define UART1_FR         (UART1_BASE + UART_FR)     /* Flag register*/
#define UART1_ILPR       (UART1_BASE + UART_ILPR)   /* IrDA low power register*/
#define UART1_IBRD       (UART1_BASE + UART_IBRD)   /* Integer baud rate dividor*/
#define UART1_FBRD       (UART1_BASE + UART_FBRD)   /* Fractional baud rate dividor*/
#define UART1_LCR        (UART1_BASE + UART_LCR)    /* Line control reg */

#define UART1_CR         (UART1_BASE + UART_CR)     /* Control reg */
#define UART1_IFLS       (UART1_BASE + UART_IFLS)   /* Interrupt level select register*/
#define UART1_IMSC       (UART1_BASE + UART_IMSC)   /* Interrupt mask set clear register*/
#define UART1_RIS        (UART1_BASE + UART_RIS)    /* Raw interrupt status register*/
#define UART1_MIS        (UART1_BASE + UART_MIS)    /* Masked interrupt status register*/
#define UART1_ICR        (UART1_BASE + UART_ICR)    /* Interrupt clear register*/
#define UART1_DMACR      (UART1_BASE + UART_DMACR)  /* DMA control register*/






/*
	** TIMER register definitions.**
*/
#define TIMER1_LOAD	    (TIMER1_BASE + 0x0)
#define TIMER1_CURRENT	    (TIMER1_BASE + 0x4)
#define TIMER1_CNTL	    (TIMER1_BASE + 0x8)
#define TIMER1_INT_CLEAR    (TIMER1_BASE + 0xC)
#define TIMER1_RIS          (TIMER1_BASE + 0x10)
#define TIMER1_MIS          (TIMER1_BASE + 0x14)
#define TIMER1_BGLOAD       (TIMER1_BASE + 0x18)

#define TIMER2_LOAD	    (TIMER2_BASE + 0x00)
#define TIMER2_CURRENT	    (TIMER2_BASE + 0x04)
#define TIMER2_CNTL	    (TIMER2_BASE + 0x08)
#define TIMER2_INT_CLEAR    (TIMER2_BASE + 0x0C)
#define TIMER2_RIS          (TIMER2_BASE + 0x10)
#define TIMER2_MIS          (TIMER2_BASE + 0x14)
#define TIMER2_BGLOAD       (TIMER2_BASE + 0x18)



/*
	GPIO's misc registers definitions.
*/
#define GPIO_SPACE_SIZE    0x1000
#define GPIO_0             0
#define GPIO_1             1
#define GPIO_2             2
#define GPIO_3             3

#define GPIO_GROUP_NUMBER  4

/*register discription*/
#define GPIO_DATA_OFFSET   0          /* gpio data register offset */

#define GPIO_DIR           0x400      /* gpio direction register */

#define DIRECTION_OUTPUT   1
#define DIRECTION_INPUT    0

#define GPIO_IS            0x404      /* gpio interrupt sense register */
#define SENSE_EDGE         0
#define SENSE_LEVEL        1

#define GPIO_IBE           0x408      /* gpio interrupt both edge register */
#define SENSE_SINGLE       0
#define SENSE_BOTH         1

#define GPIO_IEV           0x40C      /* gpio interrupt event register  */
#define EVENT_RISING_EDGE  1
#define EVENT_FALLING_EDGE 0

#define EVENT_HIGH_LEVEL   1
#define EVENT_LOW_LEVEL    0

#define GPIO_IE            0x410      /* gpio interrupt enable register  */
#define GPIO_RIS           0x414      /* gpio raw interrupt status register */
#define GPIO_MIS           0x418      /* gpio masked interrupt status register */
#define GPIO_IC            0x41C      /* gpio interrupt clear register */
#define GPIO_AFSEL         0x420      /* gpio mode control select register */
                                      /* 1: enable hardware control; */
                                      /* 0: enable software control. */




/*
 *  definitions for the UART
*/
#define SERIAL_0_BASE_ADR	UART0_BASE	/* UART 0 base address */
#define SERIAL_1_BASE_ADR	UART1_BASE	/* UART 1 base address */
#define SERIAL_2_BASE_ADR	UART2_BASE	/* UART 2 base address */

#define N_SIO_CHANNELS		AMBA_UART_CHANNELS
#define N_UART_CHANNELS		AMBA_UART_CHANNELS




/*
 * definitions for the Timer:
 * two timers clocked from same source and with the same reload overhead
 */
#define SYS_TIMER_CLEAR 	TIMER1_INT_CLEAR    /* Timer 1 Interrupt Clear */
#define SYS_TIMER_CTRL  	TIMER1_CNTL    /* Timer 1 Control */
#define SYS_TIMER_LOAD  	TIMER1_LOAD    /* Timer 1 Load */
#define SYS_TIMER_VALUE 	TIMER1_CURRENT    /* Timer 1 Value */
#define SYS_TIMER_RIS           TIMER1_RIS
#define SYS_TIMER_MIS           TIMER1_MIS
#define SYS_TIMER_BGLOAD        TIMER1_BGLOAD  

#define AUX_TIMER_CLEAR		TIMER2_INT_CLEAR    /* Timer 2 Interrupt Clear */
#define AUX_TIMER_CTRL  	TIMER2_CNTL    /* Timer 2 Control */
#define AUX_TIMER_LOAD  	TIMER2_LOAD    /* Timer 2 Load */
#define AUX_TIMER_VALUE 	TIMER2_CURRENT    /* Timer 2 Value */
#define AUX_TIMER_RIS           TIMER2_RIS
#define AUX_TIMER_MIS           TIMER2_MIS
#define AUX_TIMER_BGLOAD        TIMER2_BGLOAD

#if defined(BOARD_HI3510DEMO)
	#define SYS_TIMER_CLK	(HCLK_FREQ)    /* Frequency of counter/timer is 33MHz.*/
	#define AUX_TIMER_CLK	(HCLK_FREQ)    /* Frequency of counter/timer is 33MHz.*/
#else
	#define SYS_TIMER_CLK	(HCLK_FREQ)    /* Frequency of counter/timer is 33MHz.*/
	#define AUX_TIMER_CLK	(HCLK_FREQ)    /* Frequency of counter/timer is 33MHz.*/
#endif

#define SYS_TIMER_INT_LVL (INT_LVL_TIMER_1)
#define AUX_TIMER_INT_LVL (INT_LVL_TIMER_2)
/*
 * Clock rates depend upon CPU power and work load of application.
 * The values below are minimum and maximum allowed by the hardware.
 * Note that it takes 1 ticks to reload the 16-bit counter and we don't
 * accept values that would mean a zero reload value as we don't know what
 * that will do.
 * So:
 * min frequency = roundup(clock_rate/(max_counter_value)+1)
 * max frequency = rounddown(clock_rate/(min_counter_value)+1)
 * i.e. 		     SYS_CLK_RATE_MAX (SYS_TIMER_CLK/(1+1))
 * However, we must set maxima that are sustainable on a running
 * system. Experiments suggest that a 16MHz ECS board can sustain a
 * maximum clock rate of 16384. The values below have been
 * chosen so that there is a reasonable margin and the BSP passes the
 * test suite.
 */

#define SYS_CLK_RATE_MIN ((SYS_TIMER_CLK + 0xffffffff) / 0x100000000)
/*if cpu clock is 192KHz,then the minimum rate is 3 */
#define SYS_CLK_RATE_MAX       16384


#define AUX_CLK_RATE_MIN       ((AUX_TIMER_CLK + 0xffffffff) / 0x100000000)
#define AUX_CLK_RATE_MAX       16384
#define TIMER_RELOAD_TICKS     1






/* Watchdog frequency definition. */
#define WDG_HIGH_FREQ_CLK	32768      /* Watch dog Freqency is 32.768KHz. */
                                          /* Maybe should be redefined.  */
#define WDG_LOW_FREQ_CLK	32768
#define WDG_TIMEOUT_DEFAULT	200         /* Watch dog timeout time is 200ms. */





/*
 * remap  definition
*/

#define  REMAPOFFSET	ROM_BASE_ADRS




/* #define MPMC_SPEED_75MHZ     */
/* #define SSMC_SPEED_37MHZ     */

/* #define MPMC_SPEED_50MHZ     */
#define MPMC_SPEED_25MHZ

/* #define MPMC_SPEED_VPB    */        /* In fact it is 70MHz. */
/* #define SSMC_SPEED_VPB    */        /* In fact it is 35MHz. */

/* #define MPMC_SPEED_9600K    */
/* #define SSMC_SPEED_9600K    */










#if defined(CPU_940T) || defined(CPU_940T_T) || defined (CPU_926ES)
/*
 * All ARM 940T BSPs must define a variable sysCacheUncachedAdrs: a
 * pointer to a word that is uncached and is safe to read (i.e. has no
 * side effects).  This is used by the cacheLib code to perform a read
 * (only) to drain the write-buffer. Clearly this address must be present
 * within one of the regions created within sysPhysMemDesc, where it must
 * be marked as non-cacheable. There are many such addresses we could use
 * on the board, but we choose to use an address here that will be
 * mapped in on just about all configurations: a safe address within the
 * interrupt controller: the IRQ Enabled status register. This saves us
 * from having to define a region just for this pointer. This constant
 * defined here is used to initialise sysCacheUncachedAdrs in sysLib.c
 * and is also used by the startup code in sysALib.s and romInit.s in
 * draining the write-buffer.
 */

#define SYS_CACHE_UNCACHED_ADRS               VIC_INT_ENABLE  /* Praful ARM926 MMU needs for sync. */
#endif /* defined(CPU_940T/940T_T/CPU_926ES) */

#include "hi_intrCtl.h"

#endif /*End of __HI_BOARD_H__ */