📄 hi_board.h

📁 华为 HI3510 BOOTLOADER HIBOOT 源码包
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	#define ITCM_SIZE	0x4000		#define DTCM_BASE	(ITCM_BASE+ITCM_SIZE)	#define DTCM_SIZE	0x2000	#endif#if defined(BOARD_HI3517FPGA)||defined(BOARD_HI3517DEMO)			/*		MPMC bank 4 space, connect to SDRAM.	*/	#define ECS_MPMC_BANK_4_BASE	0x00000000	#define ECS_MPMC_BANK_4_SIZE	0x08000000		/*		Misc peripheral APB device is in this space.		Used to fill the sysPhysMemDesc[].	*/	#define ECS_PERIPHERAL_BASE	0x10000000	#define ECS_PERIPHERAL_SIZE	0x00200000		#define ECS_MPMC_CONFIG_REG_BASE	0x10110000	#define ECS_MPMC_CONFIG_REG_SIZE	0x00010000	#define ECS_DMAC_BASE	0x10130000	#define ECS_DMAC_SIZE	0x00010000	#define ECS_VIC_BASE	0x10140000	#define ECS_VIC_SIZE	0x00010000		/*** APB base address and size definitions. ***/	#define ECS_APB_BASE	0x101E0000	#define ECS_APB_SIZE	0x00020000		/*		All devices in APB.	*/		/* Base definition of system controller */			#define SYSTEM_CONTROL_BASE	ECS_APB_BASE				/** WDG definition :base address and debug definition      */		/** Added by yuanyabin 2004-5-31 according to the PXP       */		#define WDG_BASE	(ECS_APB_BASE + 0x1000)				/*** TIMER register addresses ***/		#define TIMER1_BASE	(ECS_APB_BASE + 0x00002000)		#define TIMER2_BASE	(ECS_APB_BASE + 0x00002020)						/*** GPIO register addresses ***/		#define GPIO_BASE	(ECS_APB_BASE + 0x4000)		#define GPIO_0_BASE	GPIO_BASE		#define GPIO_1_BASE	(GPIO_BASE + 0x1000)		#define GPIO_2_BASE	(GPIO_BASE + 0x2000)		#define GPIO_3_BASE	(GPIO_BASE + 0x3000)				#define GPIO_4_BASE	(ECS_APB_BASE + 0x17000)		#define GPIO_5_BASE	(ECS_APB_BASE + 0x18000)		#define GPIO_6_BASE	(ECS_APB_BASE + 0x19000)		#define GPIO_7_BASE	(ECS_APB_BASE + 0x1A000)		/** RTC definition :base address and debug definition. **/		/** Added by yuanyabin 2004-5-31 according to the PXP      */		#define	AMBA_RTC_BASE	(ECS_APB_BASE + 0x8000)				/*** Base register adress description. ***/		#define UART0_BASE	(ECS_APB_BASE + 0x11000)				#define SSP_BASE	(ECS_APB_BASE + 0x14000)		#define SSP_CLK	25000000			#define ECS_MPMC_BANK_0_BASE	0x30000000	#define ECS_MPMC_BANK_0_SIZE	0x04000000		#define ECS_MPMC_BANK_1_BASE	0x34000000	#define ECS_MPMC_BANK_1_SIZE	0x04000000			#define ZSP_IMEM_ADDRESS	(0x80000000)	#define ZSP_IMEM_SIZE	(0x40000)	#define ZSP_DMEM_ADDRESS	(0x80040000)	#define ZSP_DMEM_SIZE	(0x40000)			#define SIO_BASE	(0x80080000)	#define SIO_REG_SIZE	(0x1000)	#define USB_BASE	0xA0000000	#define USB_REG_SIZE	0x00010000	#define ARBITER_BASE	0xA0010000	#define ARBITER_REG_SIZE	0x00010000	#define SF_BASE	0x90030000	#define SF_REG_SIZE	0x00010000		#define ITCM_BASE	0x0	#define ITCM_SIZE	0x8000		#define DTCM_BASE	(ITCM_BASE+ITCM_SIZE)	#define DTCM_SIZE	0x8000	#endif	#if defined(BOARD_HI3560FPGA)||defined(BOARD_HI3560DEMO)	/*		MPMC bank 4 space, connect to SDRAM.	*/	#define ECS_MPMC_BANK_4_BASE	0x00000000	#define ECS_MPMC_BANK_4_SIZE	0x08000000		/*		Misc peripheral APB device is in this space.		Used to fill the sysPhysMemDesc[].	*/	#define ECS_PERIPHERAL_BASE	0x10000000	#define ECS_PERIPHERAL_SIZE	0x00200000		#define ECS_MPMC_CONFIG_REG_BASE	0x10110000	#define ECS_MPMC_CONFIG_REG_SIZE	0x00010000	#define VOU_BASE_ADRS	0x10120000	#define VOU_REG_SIZE	0x00010000	#define ECS_DMAC_BASE	0x10130000	#define ECS_DMAC_SIZE	0x00010000	#define ECS_VIC_BASE	0x10140000	#define ECS_VIC_SIZE	0x00010000			/*** APB base address and size definitions. ***/	#define ECS_APB_BASE	0x101E0000	#define ECS_APB_SIZE	0x00020000		/*		All devices in APB.	*/		/* Base definition of system controller */			#define SYSTEM_CONTROL_BASE	ECS_APB_BASE				/** WDG definition :base address and debug definition      */		/** Added by yuanyabin 2004-5-31 according to the PXP       */		#define WDG_BASE	(ECS_APB_BASE + 0x1000)				/*** TIMER register addresses ***/		#define TIMER1_BASE	(ECS_APB_BASE + 0x00002000)		#define TIMER2_BASE	(ECS_APB_BASE + 0x00002020)						/*** GPIO register addresses ***/		#define GPIO_BASE	(ECS_APB_BASE + 0x4000)		#define GPIO_0_BASE	GPIO_BASE		#define GPIO_1_BASE	(GPIO_BASE + 0x1000)		#define GPIO_2_BASE	(GPIO_BASE + 0x2000)		#define GPIO_3_BASE	(GPIO_BASE + 0x3000)				#define GPIO_4_BASE	(ECS_APB_BASE + 0x17000)		#define GPIO_5_BASE	(ECS_APB_BASE + 0x18000)		#define GPIO_6_BASE	(ECS_APB_BASE + 0x19000)		#define GPIO_7_BASE	(ECS_APB_BASE + 0x1A000)				/*** DES register addresses ***/		#define DES_BASE	(ECS_APB_BASE + 0x1B000)				/** RTC definition :base address and debug definition. **/		/** Added by yuanyabin 2004-5-31 according to the PXP      */		#define	AMBA_RTC_BASE	(ECS_APB_BASE + 0x8000)				/*** Base register adress description. ***/		#define UART0_BASE	(ECS_APB_BASE + 0x11000)		#define UART1_BASE	(ECS_APB_BASE + 0x12000)						#define SSP_BASE	(ECS_APB_BASE + 0x14000)		#define SSP_CLK	25000000			/*** I2C register address ***/		#define I2C_BASE	(ECS_APB_BASE + 0x16000)				#define I2C_SIZE	0x1000		#define I2C_CLK (HCLK_FREQ)		#define I2C_RATE	(30000)		/* Default bootup bank. */	#define SSMC_BANK_7_BASE	0x34000000	#define SSMC_BANK_7_SIZE	0x04000000			#define ZSP_IMEM_ADDRESS	(0x80000000)	#define ZSP_IMEM_SIZE	(0x14000)	/* only 80Kbytes */	#define ZSP_DMEM_ADDRESS	(0x80040000)	#define ZSP_DMEM_SIZE	(0x10000)	/* only 64Kbytes */			#define SIO_BASE	(0x80080000)	#define SIO_REG_SIZE	(0x00010000)			/* VIU base address definition.*/	#define	VIU_BASE_ADRS	0x90000000	#define VIU_REG_SIZE	(0x1000)			/* DSU base address and size definition.*/	#define DSU_BASE_ADRS	0x90010000	#define DSU_REG_SIZE	0x00010000		/* 2D base address definition.*/	#define TDE_BASE_ADRS 0x90010300	#define USB_BASE	0xA0000000	#define USB_REG_SIZE	0x00010000	#define ARBITER_BASE	0xA0010000	#define ARBITER_REG_SIZE	0x00010000	#define ETH_BASE	0xA0020000	#define ETH_REG_SIZE	0x00010000				#define DDRC_BASE	0x10150000	#define DDRC_SIZE	0x00010000			#define DDR_BASE	(0xf0000000)	#define DDR_SIZE	(0x04000000)		#define SSMC_BASE	0x10100000	#define SSMC_SIZE	0x00010000			#define ITCM_BASE	0x0	#define ITCM_SIZE	0x4000		#define DTCM_BASE	(ITCM_BASE+ITCM_SIZE)	#define DTCM_SIZE	0x2000		#define ATAH_BASE	0x28000000	#define ATAH_SIZE	0x04000000	#endif/*************************************************************************//* 	register addresses of all modules are defined in this section	*//*************************************************************************//*	MPMC register description: 	Hi3560 hase no MPMC controller, means has no SDRAM.*/#if defined(BOARD_HI3510FPGA)||defined(BOARD_HI3510DEMO)||defined(BOARD_HI3517FPGA)||defined(BOARD_HI3517DEMO)	#define MPMC_CONTROL                 (ECS_MPMC_CONFIG_REG_BASE)	#define MPMC_STATUS                  (ECS_MPMC_CONFIG_REG_BASE + 0x004)	#define MPMC_CONFIG                  (ECS_MPMC_CONFIG_REG_BASE + 0x008)	#define MPMC_DYNAMIC_CONTROL         (ECS_MPMC_CONFIG_REG_BASE + 0x020)	#define MPMC_DYNAMIC_REFRESH         (ECS_MPMC_CONFIG_REG_BASE + 0x024)	#define MPMC_DYNAMIC_READCONFIG      (ECS_MPMC_CONFIG_REG_BASE + 0x028)	#define MPMC_DYNAMIC_TRP             (ECS_MPMC_CONFIG_REG_BASE + 0x030)	#define MPMC_DYNAMIC_TRAS            (ECS_MPMC_CONFIG_REG_BASE + 0x034)	#define MPMC_DYNAMIC_TSREX           (ECS_MPMC_CONFIG_REG_BASE + 0x038)	#define MPMC_DYNAMIC_TWR             (ECS_MPMC_CONFIG_REG_BASE + 0x044)	#define MPMC_DYNAMIC_TRC             (ECS_MPMC_CONFIG_REG_BASE + 0x048)	#define MPMC_DYNAMIC_TRFC            (ECS_MPMC_CONFIG_REG_BASE + 0x04C)	#define MPMC_DYNAMIC_TXSR            (ECS_MPMC_CONFIG_REG_BASE + 0x050)	#define MPMC_DYNAMIC_TRRD            (ECS_MPMC_CONFIG_REG_BASE + 0x054)	#define MPMC_DYNAMIC_TMRD            (ECS_MPMC_CONFIG_REG_BASE + 0x058)	#define MPMC_DYNAMIC_TCDLR           (ECS_MPMC_CONFIG_REG_BASE + 0x05C)	#define MPMC_STATIC_EXTENDEDWAIT     (ECS_MPMC_CONFIG_REG_BASE + 0x080)	/* Here x=0..3 .*/	#define MPMC_DYNAMIC_CONFIG(x)       (ECS_MPMC_CONFIG_REG_BASE + 0x100 + x * 0x20)	#define MPMC_DYNAMIC_RASCAS(x)       (ECS_MPMC_CONFIG_REG_BASE + 0x100 + x * 0x20 + 0x4)	/* Here x=0..3 .*/	#define MPMC_STATIC_CONFIG(x)        (ECS_MPMC_CONFIG_REG_BASE + 0x200 + x * 0x20)	#define MPMC_STATIC_WAITWEN(x)       (ECS_MPMC_CONFIG_REG_BASE + 0x200 + x * 0x20 + 0x4)	#define MPMC_STATIC_WAITOEN(x)       (ECS_MPMC_CONFIG_REG_BASE + 0x200 + x * 0x20 + 0x8)	#define MPMC_STATIC_WAITRD(x)        (ECS_MPMC_CONFIG_REG_BASE + 0x200 + x * 0x20 + 0xC)	#define MPMC_STATIC_WAITPAGE(x)      (ECS_MPMC_CONFIG_REG_BASE + 0x200 + x * 0x20 + 0x10)	#define MPMC_STATIC_WAITWR(x)        (ECS_MPMC_CONFIG_REG_BASE + 0x200 + x * 0x20 + 0x14)	#define MPMC_STATIC_WAITTURN(x)      (ECS_MPMC_CONFIG_REG_BASE + 0x200 + x * 0x20 + 0x18)	/* Here x=0..4 .*/	#define MPMC_AHB_CONTROL(x)          (ECS_MPMC_CONFIG_REG_BASE + 0x400 + x * 0x20)	#define MPMC_AHB_STATUS(x)           (ECS_MPMC_CONFIG_REG_BASE + 0x400 + x * 0x20 + 0x04)	#define MPMC_AHB_TIMEOUT(x)          (ECS_MPMC_CONFIG_REG_BASE + 0x400 + x * 0x20 + 0x08)	#define SDRAMBank4BaseAddr  0x04000000	#define ModeRegAddr   0x10000       /* Define Mode Register address, used when reading from rams. */	#define EModeRegAddr  0x02000000	#define SDRAMModeRegAddr	(SDRAMBank4BaseAddr + ModeRegAddr)	#define SDRAMEModeRegAddr	(SDRAMBank4BaseAddr + EModeRegAddr)#endif#if defined(BOARD_HI3510FPGA)	#define DDRC_CONTROL	(DDRC_BASE)	#define DDRC_DYNAMIC_CONTROL	(DDRC_BASE + 0x020)	/* Here x=0..3 .*/	#define DDRC_DYNAMIC_CONFIG(x)       (DDRC_BASE + 0x100 + x * 0x20)	#define DDRC_DYNAMIC_RASCAS(x)       (DDRC_BASE + 0x100 + x * 0x20 + 0x4)	#define DDRC_DYNAMIC_REFRESH         (DDRC_BASE + 0x024)	#define DDRC_DYNAMIC_READCONFIG      (DDRC_BASE + 0x028)	#define DDRC_DYNAMIC_TRP             (DDRC_BASE + 0x030)	#define DDRC_DYNAMIC_TRAS            (DDRC_BASE + 0x034)	#define DDRC_DYNAMIC_TSREX           (DDRC_BASE + 0x038)	#define DDRC_DYNAMIC_TWR             (DDRC_BASE + 0x044)	#define DDRC_DYNAMIC_TRC             (DDRC_BASE + 0x048)	#define DDRC_DYNAMIC_TRFC            (DDRC_BASE + 0x04C)	#define DDRC_DYNAMIC_TXSR            (DDRC_BASE + 0x050)	#define DDRC_DYNAMIC_TRRD            (DDRC_BASE + 0x054)	#define DDRC_DYNAMIC_TMRD            (DDRC_BASE + 0x058)	#define DDRC_DYNAMIC_TCDLR           (DDRC_BASE + 0x05C)	#define DDREModeRegAddr  (DDR_BASE + 0x1000800)	#define DDRModeRegAddr1  (DDR_BASE + 0x0010800) 	#define DDRModeRegAddr2  (DDR_BASE + 0x0090800)			#define FLASH_TYPE_L18	/* #define FLASH_TYPE_J3  */		#ifdef FLASH_TYPE_L18		#define FLASH_PARAM_BOTTOM		/*define FLASH_PARAM_TOP */		#define FLASH_PARAM_BLOCK_SIZE      0x00008000   /* 32Kbytes per param bank, in fact there's 2banks. */		#define FLASH_PARAM_BLOCK_NUM       4	#endif	#define FLASH_BLOCK_SIZE            0x00020000   /* 128Kbytes per bank, in fact there's 2banks. */	#define FLASH_PARTS_PER_BANK        2#endif#if defined(BOARD_HI3510DEMO)	#define DDRC_CONTROL	(DDRC_BASE)	#define DDRC_DYNAMIC_CONTROL	(DDRC_BASE + 0x020)	/* Here x=0..3 .*/	#define DDRC_DYNAMIC_CONFIG(x)       (DDRC_BASE + 0x100 + x * 0x20)	#define DDRC_DYNAMIC_RASCAS(x)       (DDRC_BASE + 0x100 + x * 0x20 + 0x4)	#define DDRC_DYNAMIC_REFRESH         (DDRC_BASE + 0x024)	#define DDRC_DYNAMIC_READCONFIG      (DDRC_BASE + 0x028)	#define DDRC_DYNAMIC_TRP             (DDRC_BASE + 0x030)	#define DDRC_DYNAMIC_TRAS            (DDRC_BASE + 0x034)	#define DDRC_DYNAMIC_TSREX           (DDRC_BASE + 0x038)	#define DDRC_DYNAMIC_TWR             (DDRC_BASE + 0x044)	#define DDRC_DYNAMIC_TRC             (DDRC_BASE + 0x048)	#define DDRC_DYNAMIC_TRFC            (DDRC_BASE + 0x04C)	#define DDRC_DYNAMIC_TXSR            (DDRC_BASE + 0x050)	#define DDRC_DYNAMIC_TRRD            (DDRC_BASE + 0x054)	#define DDRC_DYNAMIC_TMRD            (DDRC_BASE + 0x058)	#define DDRC_DYNAMIC_TCDLR           (DDRC_BASE + 0x05C)	#define DDREModeRegAddr  (DDR_BASE + 0x1000800)	#define DDRModeRegAddr1  (DDR_BASE + 0x0010800) 	#define DDRModeRegAddr2  (DDR_BASE + 0x0090800)				#define FLASH_TYPE_J3			#define FLASH_BLOCK_SIZE            0x00020000   /* 128Kbytes per bank, in fact there's 2banks. */	#define FLASH_PARTS_PER_BANK        1
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