hi_board.h

华为 HI3510 BOOTLOADER HIBOOT 源码包

/******************************************************************************

  Copyright (C), 2001-2011, Hisilicon Tech. Co., Ltd.

 ******************************************************************************
  File Name     : hi_board.h
  Version       : Initial Draft
  Author        : Hisilicon multimedia software group
  Created       : 2005/06/25
  Last Modified :
  Description   : This file contains I/O address and related constants for the ECSBoard
  Function List :
  History       :
  1.Date        : 2005/06/25
    Author      : yuanyabin
    Modification: Created file

******************************************************************************/


#ifndef	__HI_BOARD_H__
#define	__HI_BOARD_H__


/*
	First is register read or write micro definition.
	We can use this definition to read or write registers.
*/

#ifndef HI_REG_READ8
	#define HI_REG_READ8(addr,result)  ((result) = *(volatile UINT8 *)(addr))
#endif

#ifndef HI_REG_READ16
	#define HI_REG_READ16(addr,result)  ((result) = *(volatile UINT16 *)(addr))
#endif

#ifndef HI_REG_READ32
	#define HI_REG_READ32(addr,result)  ((result) = *(volatile UINT32 *)(addr))
#endif

#ifndef HI_REG_WRITE8
	#define HI_REG_WRITE8(addr,result)  (*(volatile UINT8 *)(addr) = (result))
#endif

#ifndef HI_REG_WRITE16
	#define HI_REG_WRITE16(addr,result)  (*(volatile UINT16 *)(addr) = (result))
#endif

#ifndef HI_REG_WRITE32
	#define HI_REG_WRITE32(addr,result)  (*(volatile UINT32 *)(addr) = (result))
#endif




/*
	OS definitions, we always use vxWorks
*/
#define INCLUDE_VXWORKS



/*
	Board definitions. Because now we have a lot of version:
	hi3510_fpga, 
	hi3510_demo, 
	hi3517_fpga,
	hi3560_fpga,
	hi3560_demo,
	etc.
*/

#define BOARD_HI3510DEMO
/*
#define BOARD_HI3510FPGA
#define BOARD_HI3510DEMO
#define BOARD_HI3517FPGA
#define BOARD_HI3517DEMO
#define BOARD_HI3560FPGA
#define BOARD_HI3560DEMO
*/

/*
	At same time, we should control viu/vou/dsu versions.
*/
#if defined(BOARD_HI3510DEMO)
	#define INCLUDE_VIU_V1
	#define INCLUDE_VOU_V1
	#define INCLUDE_DSU_V1	

#elif defined(BOARD_HI3510FPGA)
	#define INCLUDE_VIU_V2
	#define INCLUDE_VOU_V1
	#define INCLUDE_DSU_V1	
#else
	#define INCLUDE_VIU_V2
	#define INCLUDE_VOU_V2
	#define INCLUDE_DSU_V2
#endif




/*
	Definition of the Flash connection type.
	PARALLEL:It means two Flash form a 32bits Flash array.
	else:Just one flash to form 16bits.
	
*/
#define PARALLEL           /* It means two Flash form a 32bits Flash array. */


/* 
	Board Frequency definition. Especially HCLK_FREQ.
*/
#if defined(BOARD_HI3510DEMO)
	#define HCLK_FREQ (100000000)
#else
	#define HCLK_FREQ (25000000)
#endif

/* #define HCLK_FREQ (25000000) */


/*
	ECS board memory map. 
	We use board micro definition to distinguish different memory map.
	Here we only define 
*/

#if defined(BOARD_HI3510FPGA)
	
	/*
		MPMC bank 4 space, connect to SDRAM.
	*/
	#define ECS_MPMC_BANK_4_BASE	0x00000000
	#define ECS_MPMC_BANK_4_SIZE	0x08000000
	
	/*
		Misc peripheral APB device is in this space.
		Used to fill the sysPhysMemDesc[].
	*/
	#define ECS_PERIPHERAL_BASE	0x10000000
	#define ECS_PERIPHERAL_SIZE	0x00200000
	
	#define ECS_MPMC_CONFIG_REG_BASE	0x10110000
	#define ECS_MPMC_CONFIG_REG_SIZE	0x00010000

	#define VOU_BASE_ADRS	0x10120000
	#define VOU_REG_SIZE	0x00010000

	#define ECS_DMAC_BASE	0x10130000
	#define ECS_DMAC_SIZE	0x00010000

	#define ECS_VIC_BASE	0x10140000
	#define ECS_VIC_SIZE	0x00010000

	
	/*** APB base address and size definitions. ***/
	#define ECS_APB_BASE	0x101E0000
	#define ECS_APB_SIZE	0x00020000
	
	/*
		All devices in APB.
	*/
		/* Base definition of system controller */	
		#define SYSTEM_CONTROL_BASE	ECS_APB_BASE
		
		/** WDG definition :base address and debug definition      */
		/** Added by yuanyabin 2004-5-31 according to the PXP       */
		#define WDG_BASE	(ECS_APB_BASE + 0x1000)
		
		/*** TIMER register addresses ***/
		#define TIMER1_BASE	(ECS_APB_BASE + 0x00002000)
		#define TIMER2_BASE	(ECS_APB_BASE + 0x00002020)
		
		
		/*** GPIO register addresses ***/
		#define GPIO_BASE	(ECS_APB_BASE + 0x4000)
		#define GPIO_0_BASE	GPIO_BASE
		#define GPIO_1_BASE	(GPIO_BASE + 0x1000)
		#define GPIO_2_BASE	(GPIO_BASE + 0x2000)
		#define GPIO_3_BASE	(GPIO_BASE + 0x3000)		
		#define GPIO_4_BASE	(ECS_APB_BASE + 0x17000)
		#define GPIO_5_BASE	(ECS_APB_BASE + 0x18000)
		#define GPIO_6_BASE	(ECS_APB_BASE + 0x19000)
		#define GPIO_7_BASE	(ECS_APB_BASE + 0x1A000)
		
		/*** DES register addresses ***/
		#define DES_BASE	(ECS_APB_BASE + 0x1B000)
		
		/** RTC definition :base address and debug definition. **/
		/** Added by yuanyabin 2004-5-31 according to the PXP      */
		#define	AMBA_RTC_BASE	(ECS_APB_BASE + 0x8000)
		
		/*** Base register adress description. ***/
		#define UART0_BASE	(ECS_APB_BASE + 0x11000)
		#define UART1_BASE	(ECS_APB_BASE + 0x12000)
		
		
		#define SSP_BASE	(ECS_APB_BASE + 0x14000)
		#define SSP_CLK	(HCLK_FREQ)
	
		/*** I2C register address ***/
		#define I2C_BASE	(ECS_APB_BASE + 0x16000)
		#define I2C_SIZE	0x1000
		#define I2C_CLK (HCLK_FREQ)
		#define I2C_RATE	(30000)
	
	
	#define ECS_MPMC_BANK_0_BASE	0x30000000
	#define ECS_MPMC_BANK_0_SIZE	0x04000000
	
	#define ECS_MPMC_BANK_1_BASE	0x34000000
	#define ECS_MPMC_BANK_1_SIZE	0x04000000
	
	
	#define ZSP_IMEM_ADDRESS	(0x80000000)
	#define ZSP_IMEM_SIZE	(0x40000)

	#define ZSP_DMEM_ADDRESS	(0x80040000)
	#define ZSP_DMEM_SIZE	(0x40000)
	
	
	#define SIO_BASE	(0x80080000)
	#define SIO_REG_SIZE	(0x1000)
	
	
	#define DEBLK_BASE	(0x80090000)
	#define DEBLK_REG_SIZE	(0x1000)
	
	/* VIU base address definition.*/
	#define	VIU_BASE_ADRS	0x90000000
	#define VIU_REG_SIZE	(0x1000)
	
	
	/* DSU base address and size definition.*/
	#define DSU_BASE_ADRS	0x90010000
	#define DSU_REG_SIZE	0x00010000
	
	/* 2D base address definition.*/
	#define TDE_BASE_ADRS 0x90010300


	#define USB_BASE	0xA0000000
	#define USB_REG_SIZE	0x00010000

	#define ARBITER_BASE	0xA0010000
	#define ARBITER_REG_SIZE	0x00010000

	#define SF_BASE	0xA0020000
	#define SF_REG_SIZE	0x00010000

	#define DDRC_BASE	0x10150000
	#define DDRC_SIZE	0x00010000	
	
	#define DDR_BASE	0xF0000000
	#define DDR_SIZE	0x04000000
	
	#define ITCM_BASE	0x0
	#define ITCM_SIZE	0x8000
	
	#define DTCM_BASE	(ITCM_BASE+ITCM_SIZE)
	#define DTCM_SIZE	0x8000
	
	
#endif


#if defined(BOARD_HI3510DEMO)
		/*
		MPMC bank 4 space, connect to SDRAM.
	*/
	#define ECS_MPMC_BANK_4_BASE	0x00000000
	#define ECS_MPMC_BANK_4_SIZE	0x08000000
	
	/*
		Misc peripheral APB device is in this space.
		Used to fill the sysPhysMemDesc[].
	*/
	#define ECS_PERIPHERAL_BASE	0x10000000
	#define ECS_PERIPHERAL_SIZE	0x00200000
	
	#define ECS_MPMC_CONFIG_REG_BASE	0x10110000
	#define ECS_MPMC_CONFIG_REG_SIZE	0x00010000

	#define VOU_BASE_ADRS	0x10120000
	#define VOU_REG_SIZE	0x00010000

	#define ECS_DMAC_BASE	0x10130000
	#define ECS_DMAC_SIZE	0x00010000

	#define ECS_VIC_BASE	0x10140000
	#define ECS_VIC_SIZE	0x00010000

	
	/*** APB base address and size definitions. ***/
	#define ECS_APB_BASE	0x101E0000
	#define ECS_APB_SIZE	0x00020000
	
	/*
		All devices in APB.
	*/
		/* Base definition of system controller */	
		#define SYSTEM_CONTROL_BASE	ECS_APB_BASE
		
		/** WDG definition :base address and debug definition      */
		/** Added by yuanyabin 2004-5-31 according to the PXP       */
		#define WDG_BASE	(ECS_APB_BASE + 0x1000)
		
		/*** TIMER register addresses ***/
		#define TIMER1_BASE	(ECS_APB_BASE + 0x00002000)
		#define TIMER2_BASE	(ECS_APB_BASE + 0x00002020)
		
		
		/*** GPIO register addresses ***/
		#define GPIO_BASE	(ECS_APB_BASE + 0x4000)
		#define GPIO_0_BASE	GPIO_BASE
		#define GPIO_1_BASE	(GPIO_BASE + 0x1000)
		#define GPIO_2_BASE	(GPIO_BASE + 0x2000)
		#define GPIO_3_BASE	(GPIO_BASE + 0x3000)		
		#define GPIO_4_BASE	(ECS_APB_BASE + 0x17000)
		#define GPIO_5_BASE	(ECS_APB_BASE + 0x18000)
		#define GPIO_6_BASE	(ECS_APB_BASE + 0x19000)
		#define GPIO_7_BASE	(ECS_APB_BASE + 0x1A000)
		
		/*** DES register addresses ***/
		#define DES_BASE	(ECS_APB_BASE + 0x1B000)
		
		/** RTC definition :base address and debug definition. **/
		/** Added by yuanyabin 2004-5-31 according to the PXP      */
		#define	AMBA_RTC_BASE	(ECS_APB_BASE + 0x8000)
		
		/*** Base register adress description. ***/
		#define UART0_BASE	(ECS_APB_BASE + 0x12000)
		#define UART1_BASE	(ECS_APB_BASE + 0x11000)
		
		
		#define SSP_BASE	(ECS_APB_BASE + 0x14000)
		#define SSP_CLK	(HCLK_FREQ)
	
		/*** I2C register address ***/
		#define I2C_BASE	(ECS_APB_BASE + 0x16000)
		#define I2C_SIZE	0x1000
		#define I2C_CLK (HCLK_FREQ)
		#define I2C_RATE	(30000)
	
	
	#define ECS_MPMC_BANK_0_BASE	0x30000000
	#define ECS_MPMC_BANK_0_SIZE	0x04000000
	
	#define ECS_MPMC_BANK_1_BASE	0x34000000
	#define ECS_MPMC_BANK_1_SIZE	0x04000000
	
	
	#define ZSP_IMEM_ADDRESS	(0x80000000)
	#define ZSP_IMEM_SIZE	(0x40000)

	#define ZSP_DMEM_ADDRESS	(0x80040000)
	#define ZSP_DMEM_SIZE	(0x40000)
	
	
	#define SIO_BASE	(0x80080000)
	#define SIO_REG_SIZE	(0x1000)
	
	
	#define DEBLK_BASE	(0x80090000)
	#define DEBLK_REG_SIZE	(0x1000)
	
	/* VIU base address definition.*/
	#define	VIU_BASE_ADRS	0x90000000
	#define VIU_REG_SIZE	(0x1000)
	
	
	/* DSU base address and size definition.*/
	#define DSU_BASE_ADRS	0x90010000
	#define DSU_REG_SIZE	0x00010000
	
	/* 2D base address definition.*/
	#define TDE_BASE_ADRS 0x90010300


	#define USB_BASE	0xA0000000
	#define USB_REG_SIZE	0x00010000

	#define ARBITER_BASE	0xA0010000
	#define ARBITER_REG_SIZE	0x00010000

	#define SF_BASE	0xA0020000
	#define SF_REG_SIZE	0x00010000

	#define DDRC_BASE	0x10150000
	#define DDRC_SIZE	0x00010000	
	
	#define DDR_BASE	0xF0000000
	#define DDR_SIZE	0x04000000
	
	#define ITCM_BASE	0x0