gpifburst8a.c

本光盘专为SY2200 EZ-USB FX2 开发套件配置

    {  
		ledX_rdvar = LED1_ON;	   // GPIF is still busy withthe last transfer    
    }
  }	
  else 
  {
	  	ledX_rdvar = LED0_OFF;		// LED0 is OFF: GPIF not triggered in TD_POll 
  }
}

BOOL TD_Suspend(void)				// Called before the device goes into suspend mode
{
   return(TRUE);
}

BOOL TD_Resume(void)          		// Called after the device resumes
{
   return(TRUE);
}

//-----------------------------------------------------------------------------
// Device Request hooks
//   The following hooks are called by the end point 0 device request parser.
//-----------------------------------------------------------------------------

BOOL DR_GetDescriptor(void)
{
   return(TRUE);
}

BOOL DR_SetConfiguration(void)   	// Called when a Set Configuration command is received
{

  Configuration = SETUPDAT[ 2 ];
  return( TRUE );					// Handled by user code
}

BOOL DR_GetConfiguration(void)		// Called when a Get Configuration command is received
{
   EP0BUF[0] = Configuration;
   EP0BCH = 0;
   EP0BCL = 1;
   return(TRUE);					// Handled by user code
}

BOOL DR_SetInterface(void)			// Called when a Set Interface command is received
{
   AlternateSetting = SETUPDAT[2];
   return(TRUE);					// Handled by user code
}

BOOL DR_GetInterface(void)			// Called when a Set Interface command is received
{
   EP0BUF[0] = AlternateSetting;
   EP0BCH = 0;
   EP0BCL = 1;
   return(TRUE);					// Handled by user code
}

BOOL DR_GetStatus(void)
{
   return(TRUE);
}

BOOL DR_ClearFeature(void)
{
   return(TRUE);
}

BOOL DR_SetFeature(void)
{
   return(TRUE);
}




BOOL DR_VendorCmnd( void )
{
	switch( SETUPDAT[ 1 ] )
	{ 
		case VX_A2:
    	{ // Get status of peripheral function, by doing a GPIF single read transaction
      	  // using register(s) in XDATA space, dummy read
      	  while( !( GPIFTRIG & 0x80 ) )		// poll GPIFTRIG.7 Done bit
          {
          	ledX_rdvar = LED1_ON;			// GPIF Busy
          }
          *EP0BUF = XGPIFSGLDATLX;			// trigger GPIF single byte read transaction
          while( !( GPIFTRIG & 0x80 ) )		// poll GPIFTRIG.7 Done bit
      	  {
          	ledX_rdvar = LED1_ON;			// GPIF busy
          }
		  ledX_rdvar = LED1_OFF;			// GPIF not busy anymore
		  *EP0BUF = XGPIFSGLDATLNOX;		// ...GPIF reads byte from PERIPHERAL
          EP0BCH = 0;
          EP0BCL = 1;         				// Arm endpoint with # bytes to transfer
          EP0CS |= bmHSNAK;   				// Acknowledge handshake phase of device request
		  BLINK_LED();
          break;
      }
	  case VX_A3:
      { // Tell peripheral we're going into HS mode, by doing a GPIF single write transaction
          while( !( GPIFTRIG & 0x80 ) )		// Poll GPIFTRIG.7 Done bit
		  {
          	ledX_rdvar = LED1_ON;			// GPIF busy
          }
		  ledX_rdvar = LED1_OFF;			// GPIF not busy anymore
	      XGPIFSGLDATLX = 0xA3;				// Trigger GPIF 
          *EP0BUF = 0xA3;
          EP0BCH = 0;
          EP0BCL = 1;         				// Arm endpoint with # bytes to transfer
          EP0CS |= bmHSNAK;   				// Acknowledge handshake phase of device request
		  BLINK_LED();
          break;
      }
      case VX_A4:
      { // Abort current GPIF transaction... 
          GPIFABORT = 0xFF; 
          *EP0BUF = 0xA4;
          EP0BCH = 0;
          EP0BCL = 1;         				// Arm endpoint with # bytes to transfer
          EP0CS |= bmHSNAK;   				// Acknowledge handshake phase of device request
		  BLINK_LED();
          break;
      }
	  case VX_A6:
      {   // Turn debug LED[3:0] off...
          ledX_rdvar = LED0_OFF;
          ledX_rdvar = LED1_OFF;
          ledX_rdvar = LED2_OFF;
          ledX_rdvar = LED3_OFF;
          *EP0BUF = 0xA6;
          EP0BCH = 0;
          EP0BCL = 1;         				// Arm endpoint with # bytes to transfer
          EP0CS |= bmHSNAK;   				// Acknowledge handshake phase of device request
		  BLINK_LED();
		  break;
      }
      case VX_A7:
      {   // Setup peripheral for high speed FIFO xfr(s), TC=8 bytes
          EP8GPIFTCH = 0x00;  				// setup transaction count
          EP8GPIFTCL = 0x08;  				// set EP8GPIFTC = 8
          *EP0BUF = 0xA7;
          EP0BCH = 0;
          EP0BCL = 1;         				// Arm endpoint with # bytes to transfer
          EP0CS |= bmHSNAK;   				// Acknowledge handshake phase of device request
		 BLINK_LED();
		  break;
      }
	  case VX_A8:
      {   									// Do a FIFO Rd transaction w/TC=8 into EP8
          if( !( EP2468STAT & 0x80 ) )
          { 								// EP8FF=0, when buffer is available...
            								// trigger FIFO read transaction(s), using SFR
            while( !( GPIFTRIG & 0x80 ) )	// Poll GPIFTRIG.7 Done bit
		    {
          		ledX_rdvar = LED1_ON;		// GPIF busy
            }
			ledX_rdvar = LED1_OFF;			// GPIF not busy anymore
	        GPIFTRIG = GPIFTRIGRD | GPIF_EP8; // R/W=1, EP[1:0]=FIFO_EpNum for EPx read(s)
            *EP0BUF = 0xA8;   				// return that there was a buffer available
		    BLINK_LED();
          }
          else
          {  								// If EP busy then host is behind...
             *EP0BUF = 0x00;  				// Buffer space wasn't available and we still have
             				  				// two buffers containing data 
  			 ledX_rdvar = LED3_ON;   		// Indicate buffer is not available
          }
          EP0BCH = 0;
          EP0BCL = 1;         				// Arm endpoint with # bytes to transfer
          EP0CS |= bmHSNAK;   				// Acknowledge handshake phase of device request
		  break;
      }
      case VX_A9:
      {   									// Do a FIFO Wr transaction w/TC=BC from EP2
          if( EP24FIFOFLGS & 0x02 )
          { // EP2EF=1 when FIFO is empty, 8051 didn't "pass-on" pkt.
            *EP0BUF = 0x00;   				// Buffer was empty, not available 
            ledX_rdvar = LED3_ON;  		    // Indicate empty buffer while GPIF write transaction
          }
          else
          { // EP2EF=0 when FIFO "not" empty, 8051 committed pkt.
            GPIFTRIG = GPIF_EP2;  			// R/W=0, EP[1:0]=FIFO_EpNum for EPx write(s)
            *EP0BUF = 0xA9;
            BLINK_LED();		  			// Succesful transaction
          }
          EP0BCH = 0;
          EP0BCL = 1;         				// Arm endpoint with # bytes to transfer
          EP0CS |= bmHSNAK;   				// Acknowledge handshake phase of device request
		  break;	
      }
	  case VX_AA:
      {   									// manually commit IN data to host...
          									// GPIF needs to still be pointing to EP8, last FIFO accessed
          if( EP2468STAT & 0x80 )   
          { 								// EP8F=1 when buffer is not available
             *EP0BUF = 0x00;   				// buffer wasn't available 
             ledX_rdvar = LED3_ON;   		// debug
          }
          else
          {  								// EP8F=0 when buffer is available
             EP8BCH = EP8FIFOBCH;
             EP8BCL = EP8FIFOBCL;  			// 8051 commits pkt by writing bc
             ledX_rdvar = LED3_OFF;   		// debug
             *EP0BUF = 0xAA;
          }
          EP0BCH = 0;
          EP0BCL = 1;         				// Arm endpoint with # bytes to transfer
          EP0CS |= bmHSNAK;   				// Acknowledge handshake phase of device request
		  BLINK_LED();
		  break;
      }
	  case VX_AB:
      {  // manually commit OUT data to master...
         // GPIF needs to still be pointing to EP8, last FIFO accessed
         if( EP2468STAT & 0x01 )
         { 									// EP2EF=1 when FIFO is empty, host didn't sent pkt.
             *EP0BUF = 0x00;   				// buffer was empty, not available 
             ledX_rdvar = LED3_ON;   		// debug
         }
         else
         { // EP2EF=0 when FIFO "not" empty, host sent pkt.
             EP2GPIFTCH = EP2BCH;  			// setup transaction count
             EP2GPIFTCL = EP2BCL;  			// set EP2GPIFTC = EP2BC
             EP2BCL = 0x00;  				// AUTOOUT=0, so "pass-on" pkt. to master (GPIF)
             								// once master xfr's OUT pkt, it "auto" (re)arms
             								// trigger FIFO write transaction(s), using SFR
             *EP0BUF = 0xAB;
         }
         EP0BCH = 0;
         EP0BCL = 1;         				// Arm endpoint with # bytes to transfer
         EP0CS |= bmHSNAK;   				// Acknowledge handshake phase of device request
		BLINK_LED();
		 break;
      }
	  case VX_AC:
      {  									// manually commit IN data to host...
         									// GPIF needs to still be pointing to EP8, last FIFO accessed
         if( EP2468STAT & 0x80 )   
         { 									// EP8F=1 when buffer is not available
            *EP0BUF = 0x00;   				// buffer wasn't available 
            ledX_rdvar = LED3_ON;   		// debug
         }
         else
         { // EP8F=0 when buffer is available
            INPKTEND = 0x08;    			// 8051 commits pkt by writing #8 to INPKTEND
            *EP0BUF = 0xAC;
            ledX_rdvar = LED3_OFF;   		// debug
         }
            EP0BCH = 0;
            EP0BCL = 1;         			// Arm endpoint with # bytes to transfer
            EP0CS |= bmHSNAK;   			// Acknowledge handshake phase of device request
		    BLINK_LED();
			break;
      }
	  case VX_AD:
      { 									// setup GPIF FIFO Reads w/TC=8
           *EP0BUF = 0xAD;
           EP8GPIFTCH = 0x00;  				// setup transaction count
           EP8GPIFTCL = 0x08;  				// EP8GPIFTC = 8
           EP0BCH = 0;
           EP0BCL = 1;         				// Arm endpoint with # bytes to transfer
           EP0CS |= bmHSNAK;   				// Acknowledge handshake phase of device request
		   BLINK_LED();
		   break;
      }
	  case VX_AE:
      { 									// get status of GPIF
          *EP0BUF = GPIFTRIG; 				// return status of GPIFDONE bit
          EP0BCH = 0;
          EP0BCL = 1;         				// Arm endpoint with # bytes to transfer
          EP0CS |= bmHSNAK;   				// Acknowledge handshake phase of device request
		  BLINK_LED();
          break;
      }
	  case VX_AF:
      { 					  
          *EP0BUF = 0xAF;	  				// return status of GPIFDONE bit
          EP8BCH = 0x00;      				// Commit one zerolen IN pkt
          EP8BCL = 0x00;			
          EP0BCH = 0;
          EP0BCL = 1;         				// Arm endpoint with # bytes to transfer
          EP0CS |= bmHSNAK;   				// Acknowledge handshake phase of device request
		  BLINK_LED();
          break;
      }
	  case VX_B1:
      { // examine flags...
          *EP0BUF = EP8FIFOFLGS;
          EP0BCH = 0;
          EP0BCL = 1;         				// Arm endpoint with # bytes to transfer
          EP0CS |= bmHSNAK;   				// Acknowledge handshake phase of device request
		  BLINK_LED();
		  break;
      }
	  case VX_B2:
      { // examine flags...
          *EP0BUF = EP2468STAT;
          EP0BCH = 0;
          EP0BCL = 1;         				// Arm endpoint with # bytes to transfer
          EP0CS |= bmHSNAK;   				// Acknowledge handshake phase of device request
		 BLINK_LED();
		  break;
      }
	  case VX_B3:
      { // examine flags...
          *EP0BUF = EP68FIFOFLGS;
          EP0BCH = 0;
          EP0BCL = 1;         				// Arm endpoint with # bytes to transfer
          EP0CS |= bmHSNAK;   				// Acknowledge handshake phase of device request
		  BLINK_LED();