📄 adda_isr.lst
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A51 MACRO ASSEMBLER ADDA_ISR 04/02/2007 08:52:20 PAGE 1
MACRO ASSEMBLER A51 V7.07
OBJECT MODULE PLACED IN ADDA_ISR.OBJ
ASSEMBLER INVOKED BY: C:\Keil\C51\BIN\A51.EXE ADDA_ISR.asm NOMOD51 SET(LARGE) DEBUG EP
LOC OBJ LINE SOURCE
1 ;
2 ;为了提高AD，DA性能，T4和ADC0中断使用A51编写
3 ;
4 ;$include (c8051f120.inc)
+1 5 ;---------------------------------------------------------------------------
+1 6 ;
+1 7 ;
+1 8 ;
+1 9 ;
+1 10 ; FILE NAME: C8051F120.INC
+1 11 ; TARGET MCUs: C8051F120, F121, F122, F123, F124, F125, F126, F127
+1 12 ; DESCRIPTION: Register/bit definitions for the C8051F120 product family.
+1 13 ;
+1 14 ; REVISION 1.6
+1 15 ;
+1 16 ;---------------------------------------------------------------------------
+1 17
+1 18 ;REGISTER DEFINITIONS
+1 19 ;
0080 +1 20 P0 DATA 080H ; PORT 0 LATCH
0081 +1 21 SP DATA 081H ; STACK POINTER
0082 +1 22 DPL DATA 082H ; DATA POINTER LOW BYTE
0083 +1 23 DPH DATA 083H ; DATA POINTER HIGH BYTE
0084 +1 24 SFRPAGE DATA 084H ; SFR PAGE SELECT
0085 +1 25 SFRNEXT DATA 085H ; SFR STACK NEXT PAGE
0086 +1 26 SFRLAST DATA 086H ; SFR STACK LAST PAGE
0087 +1 27 PCON DATA 087H ; POWER CONTROL
0088 +1 28 FLSTAT DATA 088H ; FLASH STATUS
0088 +1 29 CPT0CN DATA 088H ; COMPARATOR 0 CONTROL
0088 +1 30 CPT1CN DATA 088H ; COMPARATOR 1 CONTROL
0088 +1 31 TCON DATA 088H ; TIMER/COUNTER CONTROL
0089 +1 32 TMOD DATA 089H ; TIMER/COUNTER MODE
0089 +1 33 CPT0MD DATA 089H ; COMPARATOR 0 CONFIGURATION
0089 +1 34 CPT1MD DATA 089H ; COMPARATOR 1 CONFIGURATION
0089 +1 35 PLL0CN DATA 089H ; PLL CONTROL
008A +1 36 OSCICN DATA 08AH ; INTERNAL OSCILLATOR CONTROL
008A +1 37 TL0 DATA 08AH ; TIMER/COUNTER 0 LOW BYTE
008B +1 38 OSCICL DATA 08BH ; INTERNAL OSCILLATOR CALIBRATION
008B +1 39 TL1 DATA 08BH ; TIMER/COUNTER 1 LOW BYTE
008C +1 40 OSCXCN DATA 08CH ; EXTERNAL OSCILLATOR CONTROL
008C +1 41 TH0 DATA 08CH ; TIMER/COUNTER 0 HIGH BYTE
008D +1 42 TH1 DATA 08DH ; TIMER/COUNTER 1 HIGH BYTE
008D +1 43 PLL0DIV DATA 08DH ; PLL DIVIDER
008E +1 44 CKCON DATA 08EH ; CLOCK CONTROL
008E +1 45 PLL0MUL DATA 08EH ; PLL MULTIPLIER
008F +1 46 PSCTL DATA 08FH ; FLASH WRITE/ERASE CONTROL
008F +1 47 PLL0FLT DATA 08FH ; PLL FILTER
0090 +1 48 P1 DATA 090H ; PORT 1 LATCH
0091 +1 49 SSTA0 DATA 091H ; UART 0 STATUS
0091 +1 50 MAC0BL DATA 091H ; MAC0 B REGISTER LOW BYTE
0092 +1 51 MAC0BH DATA 092H ; MAC0 B REGISTER HIGH BYTE
0093 +1 52 MAC0ACC0 DATA 093H ; MAC0 ACCUMULATOR BYTE 0
0094 +1 53 MAC0ACC1 DATA 094H ; MAC0 ACCUMULATOR BYTE 1
0095 +1 54 MAC0ACC2 DATA 095H ; MAC0 ACCUMULATOR BYTE 2
0096 +1 55 SFRPGCN DATA 096H ; SFR PAGE CONTROL
0096 +1 56 MAC0ACC3 DATA 096H ; MAC0 ACCUMULATOR BYTE 3
0097 +1 57 MAC0OVR DATA 097H ; MAC0 ACCUMULATOR OVERFLOW BYTE
0097 +1 58 CLKSEL DATA 097H ; SYSTEM CLOCK SELECT
A51 MACRO ASSEMBLER ADDA_ISR 04/02/2007 08:52:20 PAGE 2
0098 +1 59 SCON0 DATA 098H ; UART 0 CONTROL
0098 +1 60 SCON1 DATA 098H ; UART 1 CONTROL
0099 +1 61 SBUF0 DATA 099H ; UART 0 DATA BUFFER
0099 +1 62 SBUF1 DATA 099H ; UART 1 DATA BUFFER
009A +1 63 SPI0CFG DATA 09AH ; SPI CONFIGURATION
009A +1 64 CCH0MA DATA 09AH ; CACHE MISS ACCUMULATOR
009B +1 65 SPI0DAT DATA 09BH ; SPI DATA
009C +1 66 P4MDOUT DATA 09CH ; PORT 4 OUTPUT MODE CONFIGURATION
009D +1 67 P5MDOUT DATA 09DH ; PORT 5 OUTPUT MODE CONFIGURATION
009D +1 68 SPI0CKR DATA 09DH ; SPI CLOCK RATE CONTROL
009E +1 69 P6MDOUT DATA 09EH ; PORT 6 OUTPUT MODE CONFIGURATION
009F +1 70 P7MDOUT DATA 09FH ; PORT 7 OUTPUT MODE CONFIGURATION
00A0 +1 71 P2 DATA 0A0H ; PORT 2 LATCH
00A1 +1 72 EMI0TC DATA 0A1H ; EMIF TIMING CONTROL
00A1 +1 73 CCH0CN DATA 0A1H ; CACHE CONTROL
00A2 +1 74 EMI0CN DATA 0A2H ; EMIF CONTROL
00A2 +1 75 CCH0TN DATA 0A2H ; CACHE TUNING
00A3 +1 76 EMI0CF DATA 0A3H ; EMIF CONFIGURATION
00A3 +1 77 CCH0LC DATA 0A3H ; CACHE LOCK
00A4 +1 78 P0MDOUT DATA 0A4H ; PORT 0 OUTPUT MODE CONFIGURATION
00A5 +1 79 P1MDOUT DATA 0A5H ; PORT 1 OUTPUT MODE CONFIGURATION
00A6 +1 80 P2MDOUT DATA 0A6H ; PORT 2 OUTPUT MODE CONFIGURATION
00A7 +1 81 P3MDOUT DATA 0A7H ; PORT 3 OUTPUT MODE CONFIGURATION
00A8 +1 82 IE DATA 0A8H ; INTERRUPT ENABLE
00A9 +1 83 SADDR0 DATA 0A9H ; UART 0 SLAVE ADDRESS
00AD +1 84 P1MDIN DATA 0ADH ; PORT 1 INPUT MODE
00B0 +1 85 P3 DATA 0B0H ; PORT 3 LATCH
00B1 +1 86 PSBANK DATA 0B1H ; FLASH BANK SELECT
00B7 +1 87 FLACL DATA 0B7H ; FLASH ACCESS LIMIT
00B7 +1 88 FLSCL DATA 0B7H ; FLASH SCALE
00B8 +1 89 IP DATA 0B8H ; INTERRUPT PRIORITY
00B9 +1 90 SADEN0 DATA 0B9H ; UART 0 SLAVE ADDRESS MASK
00BA +1 91 AMX0CF DATA 0BAH ; ADC0 MULTIPLEXER CONFIGURATION
00BA +1 92 AMX2CF DATA 0BAH ; ADC2 MULTIPLEXER CONFIGURATION
00BB +1 93 AMX0SL DATA 0BBH ; ADC0 MULTIPLEXER CHANNEL SELECT
00BB +1 94 AMX2SL DATA 0BBH ; ADC2 MULTIPLEXER CHANNEL SELECT
00BC +1 95 ADC0CF DATA 0BCH ; ADC0 CONFIGURATION
00BC +1 96 ADC2CF DATA 0BCH ; ADC2 CONFIGURATION
00BE +1 97 ADC0L DATA 0BEH ; ADC0 DATA WORD LOW BYTE
00BE +1 98 ADC2 DATA 0BEH ; ADC2DATA WORD
00BF +1 99 ADC0H DATA 0BFH ; ADC0 DATA WORD HIGH BYTE
00C0 +1 100 MAC0STA DATA 0C0H ; MAC0 STATUS
00C0 +1 101 SMB0CN DATA 0C0H ; SMBUS CONTROL
00C1 +1 102 MAC0AL DATA 0C1H ; MAC0 A REGISTER LOW BYTE
00C1 +1 103 SMB0STA DATA 0C1H ; SMBUS STATUS
00C2 +1 104 MAC0AH DATA 0C2H ; MAC0 A REGISTER HIGH BYTE
00C2 +1 105 SMB0DAT DATA 0C2H ; SMBUS DATA
00C3 +1 106 MAC0CF DATA 0C3H ; MAC0 CONFIGURATION REGISTER
00C3 +1 107 SMB0ADR DATA 0C3H ; SMBUS SLAVE ADDRESS
00C4 +1 108 ADC0GTL DATA 0C4H ; ADC0 GREATER-THAN LOW BYTE
00C4 +1 109 ADC2GT DATA 0C4H ; ADC2 GREATER-THAN
00C5 +1 110 ADC0GTH DATA 0C5H ; ADC0 GREATER-THAN HIGH BYTE
00C6 +1 111 ADC0LTL DATA 0C6H ; ADC0 LESS-THAN LOW BYTE
00C6 +1 112 ADC2LT DATA 0C6H ; ADC2 LESS-THAN
00C7 +1 113 ADC0LTH DATA 0C7H ; ADC0 LESS-THAN HIGH BYTE
00C8 +1 114 P4 DATA 0C8H ; PORT 4 LATCH
00C8 +1 115 TMR2CN DATA 0C8H ; TIMER/COUNTER 2 CONTROL
00C8 +1 116 TMR3CN DATA 0C8H ; TIMER 3 CONTROL
00C8 +1 117 TMR4CN DATA 0C8H ; TIMER/COUNTER 4 CONTROL
00C9 +1 118 TMR2CF DATA 0C9H ; TIMER/COUNTER 2 CONFIGURATION
00C9 +1 119 TMR3CF DATA 0C9H ; TIMER 3 CONFIGURATION
00C9 +1 120 TMR4CF DATA 0C9H ; TIMER/COUNTER 4 CONFIGURATION
00CA +1 121 RCAP2L DATA 0CAH ; TIMER/COUNTER 2 CAPTURE/RELOAD LOW BYTE
00CA +1 122 RCAP3L DATA 0CAH ; TIMER 3 CAPTURE/RELOAD LOW BYTE
00CA +1 123 RCAP4L DATA 0CAH ; TIMER/COUNTER 4 CAPTURE/RELOAD LOW BYTE
00CB +1 124 RCAP2H DATA 0CBH ; TIMER/COUNTER 2 CAPTURE/RELOAD HIGH BYTE
A51 MACRO ASSEMBLER ADDA_ISR 04/02/2007 08:52:20 PAGE 3
00CB +1 125 RCAP3H DATA 0CBH ; TIMER 3 CAPTURE/RELOAD HIGH BYTE
00CB +1 126 RCAP4H DATA 0CBH ; TIMER/COUNTER 4 CAPTURE/RELOAD HIGH BYTE
00CC +1 127 TMR2L DATA 0CCH ; TIMER/COUNTER 2 LOW BYTE
00CC +1 128 TMR3L DATA 0CCH ; TIMER 3 LOW BYTE
00CC +1 129 TMR4L DATA 0CCH ; TIMER/COUNTER 4 LOW BYTE
00CD +1 130 TMR2H DATA 0CDH ; TIMER/COUNTER 2 HIGH BYTE
00CD +1 131 TMR3H DATA 0CDH ; TIMER 3 HIGH BYTE
00CD +1 132 TMR4H DATA 0CDH ; TIMER/COUNTER 4 HIGH BYTE
00CE +1 133 MAC0RNDL DATA 0CEH ; MAC0 ROUNDING REGISTER LOW BYTE
00CF +1 134 MAC0RNDH DATA 0CFH ; MAC0 ROUNDING REGISTER HIGH BYTE
00CF +1 135 SMB0CR DATA 0CFH ; SMBUS CLOCK RATE
00D0 +1 136 PSW DATA 0D0H ; PROGRAM STATUS WORD
00D1 +1 137 REF0CN DATA 0D1H ; VOLTAGE REFERENCE CONTROL
00D2 +1 138 DAC0L DATA 0D2H ; DAC0 LOW BYTE
00D2 +1 139 DAC1L DATA 0D2H ; DAC1 LOW BYTE
00D3 +1 140 DAC0H DATA 0D3H ; DAC0 HIGH BYTE
00D3 +1 141 DAC1H DATA 0D3H ; DAC1 HIGH BYTE
00D4 +1 142 DAC0CN DATA 0D4H ; DAC0 CONTROL
00D4 +1 143 DAC1CN DATA 0D4H ; DAC1 CONTROL
00D8 +1 144 P5 DATA 0D8H ; PORT 5 LATCH
00D8 +1 145 PCA0CN DATA 0D8H ; PCA CONTROL
00D9 +1 146 PCA0MD DATA 0D9H ; PCA MODE
00DA +1 147 PCA0CPM0 DATA 0DAH ; PCA MODULE 0 MODE
00DB +1 148 PCA0CPM1 DATA 0DBH ; PCA MODULE 1 MODE REGISTER
00DC +1 149 PCA0CPM2 DATA 0DCH ; PCA MODULE 2 MODE
00DD +1 150 PCA0CPM3 DATA 0DDH ; PCA MODULE 3 MODE
00DE +1 151 PCA0CPM4 DATA 0DEH ; PCA MODULE 4 MODE
00DF +1 152 PCA0CPM5 DATA 0DFH ; PCA MODULE 5 MODE
00E0 +1 153 ACC DATA 0E0H ; ACCUMULATOR
00E1 +1 154 XBR0 DATA 0E1H ; PORT I/O CROSSBAR CONTROL 0
00E1 +1 155 PCA0CPL5 DATA 0E1H ; PCA MODULE 5 CAPTURE/COMPARE LOW BYTE
00E2 +1 156 PCA0CPH5 DATA 0E2H ; PCA MODULE 5 CAPTURE/COMPARE HIGH BYTE
00E2 +1 157 XBR1 DATA 0E2H ; PORT I/O CROSSBAR CONTROL 1
00E3 +1 158 XBR2 DATA 0E3H ; PORT I/O CROSSBAR CONTROL 2
00E6 +1 159 EIE1 DATA 0E6H ; EXTENDED INTERRUPT ENABLE 1
00E7 +1 160 EIE2 DATA 0E7H ; EXTENDED INTERRUPT ENABLE 2
00E8 +1 161 ADC0CN DATA 0E8H ; ADC0 CONTROL
00E8 +1 162 ADC2CN DATA 0E8H ; ADC2 CONTROL
00E8 +1 163 P6 DATA 0E8H ; PORT 6 LATCH
00E9 +1 164 PCA0CPL2 DATA 0E9H ; PCA MODULE 2 CAPTURE/COMPARE LOW BYTE
00EA +1 165 PCA0CPH2 DATA 0EAH ; PCA MODULE 2 CAPTURE/COMPARE HIGH BYTE
00EB +1 166 PCA0CPL3 DATA 0EBH ; PCA MODULE 3 CAPTURE/COMPARE LOW BYTE
00EC +1 167 PCA0CPH3 DATA 0ECH ; PCA MODULE 3 CAPTURE/COMPARE HIGH BYTE
00ED +1 168 PCA0CPL4 DATA 0EDH ; PCA MODULE 4 CAPTURE/COMPARE LOW BYTE
00EE +1 169 PCA0CPH4 DATA 0EEH ; PCA MODULE 4 CAPTURE/COMPARE HIGH BYTE
00EF +1 170 RSTSRC DATA 0EFH ; RESET SOURCE
00F0 +1 171 B DATA 0F0H ; B REGISTER
00F6 +1 172 EIP1 DATA 0F6H ; EXTERNAL INTERRUPT PRIORITY 1
00F7 +1 173 EIP2 DATA 0F7H ; EXTERNAL INTERRUPT PRIORITY 2
00F8 +1 174 P7 DATA 0F8H ; PORT 7 LATCH
00F8 +1 175 SPI0CN DATA 0F8H ; SPI CONTROL
00F9 +1 176 PCA0L DATA 0F9H ; PCA COUNTER LOW BYTE
00FA +1 177 PCA0H DATA 0FAH ; PCA COUNTER HIGH BYTE
00FB +1 178 PCA0CPL0 DATA 0FBH ; PCA MODULE 0 CAPTURE/COMPARE LOW BYTE
00FC +1 179 PCA0CPH0 DATA 0FCH ; PCA MODULE 0 CAPTURE/COMPARE HIGH BYTE
00FD +1 180 PCA0CPL1 DATA 0FDH ; PCA MODULE 1 CAPTURE/COMPARE LOW BYTE
00FE +1 181 PCA0CPH1 DATA 0FEH ; PCA MODULE 1 CAPTURE/COMPARE HIGH BYTE
00FF +1 182 WDTCN DATA 0FFH ; WATCHDOG TIMER CONTROL
+1 183
+1 184 ;
+1 185 ;------------------------------------------------------------------------------
+1 186 ;BIT DEFINITIONS
+1 187 ;
+1 188 ; TCON 088H
008F +1 189 TF1 BIT 08FH ; TIMER 1 OVERFLOW FLAG
008E +1 190 TR1 BIT 08EH ; TIMER 1 ON/OFF CONTROL
A51 MACRO ASSEMBLER ADDA_ISR 04/02/2007 08:52:20 PAGE 4
008D +1 191 TF0 BIT 08DH ; TIMER 0 OVERFLOW FLAG
008C +1 192 TR0 BIT 08CH ; TIMER 0 ON/OFF CONTROL
008B +1 193 IE1 BIT 08BH ; EXT. INTERRUPT 1 EDGE FLAG
008A +1 194 IT1 BIT 08AH ; EXT. INTERRUPT 1 TYPE
0089 +1 195 IE0 BIT 089H ; EXT. INTERRUPT 0 EDGE FLAG
0088 +1 196 IT0 BIT 088H ; EXT. INTERRUPT 0 TYPE
+1 197
+1 198 ; CPT0CN 088H
008F +1 199 CP0EN BIT 08FH ; COMPARATOR 0 ENABLE
008E +1 200 CP0OUT BIT 08EH ; COMPARATOR 0 OUTPUT
008D +1 201 CP0RIF BIT 08DH ; COMPARATOR 0 RISING EDGE INTERRUPT
008C +1 202 CP0FIF BIT 08CH ; COMPARATOR 0 FALLING EDGE INTERRUPT
008B +1 203 CP0HYP1 BIT 08BH ; COMPARATOR 0 POSITIVE HYSTERISIS 1
008A +1 204 CP0HYP0 BIT 08AH ; COMPARATOR 0 POSITIVE HYSTERISIS 0
0089 +1 205 CP0HYN1 BIT 089H ; COMPARATOR 0 NEGATIVE HYSTERISIS 1
0088 +1 206 CP0HYN0 BIT 088H ; COMPARATOR 0 NEGATIVE HYSTERISIS 0
+1 207
+1 208 ; CPT1CN 088H
008F +1 209 CP1EN BIT 08FH ; COMPARATOR 1 ENABLE
008E +1 210 CP1OUT BIT 08EH ; COMPARATOR 1 OUTPUT
008D +1 211 CP1RIF BIT 08DH ; COMPARATOR 1 RISING EDGE INTERRUPT
008C +1 212 CP1FIF BIT 08CH ; COMPARATOR 1 FALLING EDGE INTERRUPT
008B +1 213 CP1HYP1 BIT 08BH ; COMPARATOR 1 POSITIVE HYSTERISIS 1
008A +1 214 CP1HYP0 BIT 08AH ; COMPARATOR 1 POSITIVE HYSTERISIS 0
0089 +1 215 CP1HYN1 BIT 089H ; COMPARATOR 1 NEGATIVE HYSTERISIS 1
0088 +1 216 CP1HYN0 BIT 088H ; COMPARATOR 1 NEGATIVE HYSTERISIS 0
+1 217
+1 218 ; FLSTAT 088H
0088 +1 219 FLHBUSY BIT 088H ; FLASH BUSY
+1 220
+1 221 ; SCON0 098H
009F +1 222 SM00 BIT 09FH ; UART 0 MODE 0
009E +1 223 SM10 BIT 09EH ; UART 0 MODE 1
009D +1 224 SM20 BIT 09DH ; UART 0 MULTIPROCESSOR EN
009C +1 225 REN0 BIT 09CH ; UART 0 RX ENABLE
009B +1 226 TB80 BIT 09BH ; UART 0 TX BIT 8
009A +1 227 RB80 BIT 09AH ; UART 0 RX BIT 8
0099 +1 228 TI0 BIT 099H ; UART 0 TX INTERRUPT FLAG
0098 +1 229 RI0 BIT 098H ; UART 0 RX INTERRUPT FLAG
+1 230
+1 231 ; SCON1 098H
009F +1 232 S1MODE BIT 09FH ; UART 1 MODE
009D +1 233 MCE1 BIT 09DH ; UART 1 MCE
009C +1 234 REN1 BIT 09CH ; UART 1 RX ENABLE
009B +1 235 TB81 BIT 09BH ; UART 1 TX BIT 8
009A +1 236 RB81 BIT 09AH ; UART 1 RX BIT 8
0099 +1 237 TI1 BIT 099H ; UART 1 TX INTERRUPT FLAG
0098 +1 238 RI1 BIT 098H ; UART 1 RX INTERRUPT FLAG
+1 239
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