init_44b0.s

包含原理图、源程序与详细操作说明 汇编语言编写

;    ASCII  INVERT  in DATA ADDRESS,  OUT  UART0 ASCII
;
;************************************************************************************************************************    
uart0    
	stmfd r13!, {r10,r11,r12}
  
  
BWSCON_cfg  EQU   0x11110002  ;Bank0=16bit BootRom(AT29LV160DB) :0x0

;							 0001 0001 0001 0001 0000 0000 0000 0010
;							 ||||								 |||__0 = Little endian 1 = Big endian
;							 ||||								 ||
;							 ||||								 |____Indicates data bus width for bank 0 (read only)
;							 ||||									  00 = 8-bit 01 = 16-bit, 10 = 32-bit
;							 ||||									  The states are selected by OM[1:0] pins
;							 ||||
;							 |||____These two bits determine data bus width for bank 7
;							 ||	   	00 = 8-bit 01 = 16-bit, 10 = 32-bit
;							 || 
;							 ||_____This bit determines WAIT status for bank 7
;							 |	   	(If bank7 has DRAM or SDRAM, WAIT function is not supported)
;							 |		0 = WAIT disable 1 = WAIT enable
;							 |
;							 |______This bit determines SRAM for using UB/LB for bank 7
;								 	0 = Not using UB/LB ( Pin[14:11] is dedicated nWBE[3:0] )
;								 	1 = Using UB/LB ( Pin[14:11] is dedicated nBE[3:0] )
;----------------------------------------------------------------------------------------------------------------
;                  ||||||--	 Bank1=low 8bit D12               :0x4
;                  |||||---	 Bank2=8bit  NAND-Flash(KM29U128T):0x2
;                  ||||----	 Bank3=16bit Expend               :0x6
;                  |||-----	 Bank4=16bit Expend		  		  :0x8
;                  ||------	 Bank5=16bit ISA                  :0xA
;                  |-------  Bank6=16bit SDRAM                :0xc
;                  --------  Bank7=16bit NoUsed 
;							 Bank0:29LV160	 

;*********************************************MEMORY CONTROL PARAMETERS***************************************************

;When MCLK=66MHz,1clk=0.0152us=15.2ns
;Bank 0 parameter for Monitor Rom

                GBLS    BDRAMTYPE
BDRAMTYPE	SETS    "SDRAM"
B0_Tacs		EQU	0x0	;0clk	Address set-up before nGCSn
					;		00 = 0 clock 			01 = 1 clock		10 = 2 clocks 	11 = 4 clocks
					
B0_Tcos		EQU	0x0	;0clk	Chip selection set-up nOE
					;		00 = 0 clock 			01 = 1 clock		10 = 2 clocks 	11 = 4 clocks
					
B0_Tacc		EQU	0x6	;10clk	Access cycle
					;		000 = 1 clock 			001 = 2 clocks		010 = 3 clocks 	011 = 4 clocks
					;		100 = 6 clocks 			101 = 8 clocks		110 = 10 clocks 111 = 14 clocks
					
B0_Tcoh		EQU	0x0	;0clk	Chip selection hold on nOE
					;		00 = 0 clock 			01 = 1 clock		10 = 2 clocks 	11 = 4 clocks
					
B0_Tah		EQU	0x0	;0clk	Address holding time after nGCSn
					;		00 = 0 clock 			01 = 1 clock		10 = 2 clocks 	11 = 4 clocks
					
B0_Tacp		EQU	0x0	;0clk	Page mode access cycle @ Page mode
					;		00 = 2 clocks 			01 = 3 clocks		10 = 4 clocks 	11 = 6 clocks
					
B0_PMC		EQU	0x0	;normal(1data)	Page mode configuration
					;		00 = normal (1 data) 	01 = 4 data			10 = 8 data 	11 = 16 data
					

;Bank 1 parameter
B1_Tacs		EQU	0x3		;4clk
B1_Tcos		EQU	0x3		;4clk
B1_Tacc		EQU	0x7		;14clk
B1_Tcoh		EQU	0x3		;4clk
B1_Tah		EQU	0x3		;4clk
B1_Tacp		EQU	0x3		;6clk
B1_PMC		EQU	0x0		;normal(1data)

;Bank 2 parameter 
B2_Tacs		EQU	0x1		;4clk
B2_Tcos		EQU	0x2		;4clk
B2_Tacc		EQU	0x7		;14clk
B2_Tcoh		EQU	0x2		;4clk
B2_Tah		EQU	0x2		;4clk
B2_Tacp		EQU	0x3		;6clk
B2_PMC		EQU	0x0		;normal(1data)

;Bank 3 parameter 
B3_Tacs		EQU	0x1		;(Address set-up before nGCSn)
B3_Tcos		EQU	0x2		;(Chip selection set-up nOE)
B3_Tacc		EQU	0x7		;14clk(Access cycle)
B3_Tcoh		EQU	0x2		;(Chip selection hold on nOE)
B3_Tah		EQU	0x2		;(Address holding time after nGCSn)
B3_Tacp		EQU	0x3		;(Page mode access cycle @ Page mode)
B3_PMC		EQU	0x0		;normal(1data)

;Bank 4 parameter
B4_Tacs		EQU	0x3		;4clk
B4_Tcos		EQU	0x4		;4clk
B4_Tacc		EQU	0x6		;12clk
B4_Tcoh		EQU	0x3		;4clk
B4_Tah		EQU	0x3		;4clk
B4_Tacp		EQU	0x3		;6clk
B4_PMC		EQU	0x0		;normal(1data)

;Bank 5 parameter
B5_Tacs		EQU	0x3		;4clk	
B5_Tcos		EQU	0x3		;4clk
B5_Tacc		EQU	0x7		;14clk	
B5_Tcoh		EQU	0x3		;4clk
B5_Tah		EQU	0x3		;4clk	
B5_Tacp		EQU	0		;2clk
B5_PMC		EQU	0x0		;normal(1data)

;************************************************************************************************************************    

;Bank 6(if SROM) parameter
;B6_Tacs		EQU	0x3	;4clk	Address set-up before nGCS
						;		00 = 0 clock 	01 = 1 clock 	10 = 2 clocks 	11 = 4clocks
						
;B6_Tcos		EQU	0x3	;4clk	Chip selection set-up nOE
						;		00 = 0 clock 	01 = 1 clock 	10 = 2 clocks 	11 = 4clocks
						
;B6_Tacc		EQU	0x7	;14clk	Access cycle
						;		000 = 1 clock 	001 = 2 clocks	010 = 3 clocks 	011 = 4 clocks
						;		100 = 6 clocks 	101 = 8 clocks	110 = 10 clocks 111 = 14 clocks
						
;B6_Tcoh		EQU	0x3	;4clk	Chip selection hold on nOE
						;		00 = 0 clock 	01 = 1 clock	10 = 2 clocks 	11 = 4 clocks
						
;B6_Tah			EQU	0x3	;4clk	Address hold time on nGCSn
						;		00 = 0 clock 	01 = 1clock 	10 = 2 clocks 	11 = 4 clocks
						
;B6_Tacp		EQU	0x3	;6clk	Page mode access cycle @ Page mode
						;		00 = 2 clocks 	01 = 3 clocks	10 = 4 clocks 	11 = 6 clocks
						
;B6_PMC			EQU	0x0	;normal(1data)	Page mode configuration
						;				00 = normal (1 data) 			01 = 4 consecutive accesses
						;				10 = 8 consecutive accesses 	11 = 16 consecutive accesses

;Bank 7(if SROM) parameter
;B7_Tacs		EQU	0x3	;4clk
;B7_Tcos		EQU	0x3	;4clk
;B7_Tacc		EQU	0x7	;14clk
;B7_Tcoh		EQU	0x3	;4clk
;B7_Tah			EQU	0x3	;4clk
;B7_Tacp		EQU	0x3	;6clk
;B7_PMC			EQU	0x0	;normal(1data)

;************************************************************************************************************************    

;Bank 6 parameter
	[ BDRAMTYPE="DRAM"	;MT=01(FP DRAM) or 10(EDO DRAM) 
B6_MT		EQU	0x2	;EDO DRAM	These two bits determine the memory type for bank6 and bank7
					;			00 = ROM or SRAM 	01 = FP DRAM	10 = EDO DRAM 	11 = Sync. DRAM
					
B6_Trcd		EQU	0x1	;2clk		RAS to CAS delay
					;			00 = 1 clock 		01 = 2 clocks	10 = 3 clocks 	11 = 4 clocks
					
B6_Tcas		EQU	0x1	;2clk		CAS pulse width
					;			0 = 1 clock 		1 = 2 clocks
					
B6_Tcp		EQU	0x1	;2clk		CAS pre-charge
					;			0 = 1 clock 		1 = 2 clocks
					
B6_CAN		EQU	0x2	;10bit		Column address number
					;			00 = 8-bit 			01 = 9-bit		10 = 10-bit 	11 = 11-bit
					
	| ;"SDRAM"		;MT=11(SDRAM)
B6_MT		EQU	0x3	;SDRAM
B6_Trcd		EQU	0x0	;2clk
B6_SCAN		EQU	0x1	;9bit
	]

;Bank 7 parameter
	[ BDRAMTYPE="DRAM"	;MT=01(FP DRAM) or 10(EDO DRAM) 
B7_MT		EQU	0x2	;EDO DRAM
B7_Trcd		EQU	0x1	;2clk
B7_Tcas		EQU	0x1	;2clk
B7_Tcp		EQU	0x1	;2clk
B7_CAN		EQU	0x2	;10bit
	| ;"SDRAM"		;MT=11(SDRAM)
B7_MT		EQU	0x3	;SDRAM
B7_Trcd		EQU	0x0	;2clk
B7_SCAN		EQU	0x0	;8bit
	]

;************************************************************************************************************************    
;		REFRESH parameter

REFEN		EQU	0x1	;Refresh enable		DRAM/SDRAM Refresh Enable
					;					0 = Disable 			1 = Enable(self or CBR/auto refresh)
					
TREFMD		EQU	0x0	;CBR(CAS before RAS)/Auto refresh	
					;					DRAM/SDRAM Refresh Mode
					;					0 = CBR/Auto Refresh 	1 = Self Refresh
					;			In self-refresh time, the DRAM/SDRAM control signals are driven to the appropriate level.
					
Trp			EQU	0x1	;3clk			DRAM/SDRAM RAS pre-charge Time
					;				DRAM :	00 = 1.5 clocks 	01 = 2.5 clocks 	10 = 3.5 clocks 	11 = 4.5 clocks
					;				SDRAM:	00 = 2 clocks 		01 = 3 clocks 		10 = 4 clocks 		11 = Not support

Trc			EQU	0x1	;5clk			SDRAM RC minimum Time
					;						00 = 4 clocks 		01 = 5 clocks 		10 = 6 clocks 		11 = 7 clocks

Tchr		EQU	0x2	;3clk			CAS Hold Time(DRAM)
					;						00 = 1 clock 		01 = 2 clocks 		10 = 3 clocks 		11 = 4 clocks
					
REFCNT		EQU	1425;1019	;period=15.6us, MCLK=66Mhz
					;				DRAM/SDRAM refresh count value. Please, refer to chap. 6 DRAM
					;				refresh controller bus priority section.
					;				Refresh period = (211-refresh_count+1)/MCLK
					;					Ex) If refresh period is 15.6 us and MCLK is 60 MHz,
					;						the refresh count is as follows;
					;						refresh count = 211 + 1 - 60x15.6 = 1113
					
;************************************************************************************************************************    

SMRDATA DATA
    DCD BWSCON_cfg
 	DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))	;GCS0
	DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))	;GCS1 
	DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))	;GCS2
	DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))	;GCS3
	DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))	;GCS4
	DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))	;GCS5
	[ BDRAMTYPE="DRAM" 
	    DCD ((B6_MT<<15)+(B6_Trcd<<4)+(B6_Tcas<<3)+(B6_Tcp<<2)+(B6_CAN))	;GCS6 check the MT value in parameter.a
	    DCD ((B7_MT<<15)+(B7_Trcd<<4)+(B7_Tcas<<3)+(B7_Tcp<<2)+(B7_CAN))	;GCS7
	| ;"SDRAM"
		DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))	;GCS6
		DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))	;GCS7
	]
	DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)	;REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019
	DCD 0x10			;SCLK power down mode, BANKSIZE 32M/32M
	DCD 0x20			;MRSR6 CL=2clk
	DCD 0x20			;MRSR7
	
 
    
HandlerUndef   
    b .
HandlerSWI     
    b .
HandlerPabort  
    b .
HandlerDabort  
    b .		    
HandlerIRQ
    b .
HandlerFIQ	
	b .
	
	END