init_44b0.s

包含原理图、源程序与详细操作说明 汇编语言编写

;	Interrupt Control

INTPND	    EQU	0x01e00004
INTMOD	    EQU	0x01e00008
INTMSK	    EQU	0x01e0000c
I_ISPR	    EQU	0x01e00020
I_CMST	    EQU	0x01e0001c

;	Watchdog timer

WTCON	    EQU	0x01d30000

;	Clock Controller

PLLCON	    EQU	0x01d80000
CLKCON	    EQU	0x01d80004
LOCKTIME    EQU	0x01d8000c
	
;	Memory Controller

REFRESH	    EQU 0x01c80024

;	porta  controller

PCONA  EQU  0x01d20000
PDATA  EQU  0x1d200004

; 	UART

RULCON0   	EQU  0x1d00000
RUCON0		EQU  0x1d00004
RUFCON0		EQU  0x1d00008
RUMCON0		EQU  0x1d0000c
RUTRSTAT0	EQU  0x1d00010
RUERSTAT0	EQU  0x1d00014
RUFSTAT0 	EQU  0x1d00018
RUMSTAT0	EQU  0x1d0001C
RUBRDIV0	EQU  0x1d00028


;rPCONE		EQU		0x1d20028
;rPDATE		EQU		0x1d2002c
;rPUPE 		EQU		0x1d20030





 AREA    Init,CODE,READONLY

	 
; IMPORT __use_no_semihosting_swi

    ENTRY 
    b ResetHandler  ;for debug
    b HandlerUndef  ;handlerUndef
    b HandlerSWI    ;SWI interrupt handler
    b HandlerPabort ;handlerPAbort
    b HandlerDabort ;handlerDAbort
    b .		    	;handlerReserved
    b HandlerIRQ
    b HandlerFIQ

ResetHandler
    ldr	    r0,=WTCON	    ;watch dog disable 
    ldr	    r1,=0x0 		;Bit[15..8]	the prescaler value. 	The valid range is from 0 to (28-1)
    str	    r1,[r0]			;Bit[7..6]	Reserved.	These two bits must be 00 in normal operation.
    						;Bit[5]		Enable or disable bit of watchdog timer.
							;			0 = Disable watchdog timer
							;			1 = Enable watchdog timer
							;Bit[4..3]	This two bits determines the clock division factor
							;			00: 1/16 	01: 1/32	10: 1/64 	11: 1/128
							;Bit[2]		Enable or disable bit of the interrupt.
							;			0 = Disable interrupt generation	1 = Enable interrupt generation
							;Bit[1]		Reserved.	This bit must be 0 in normal operation
							;Bit[0]		Enable or disable bit of watchdog timer output for reset signal
							;			1: asserts reset signal of the S3C44B0X at watchdogtime-out
							;			0: disables the reset function of the watchdog timer.
    						
	;******* zdy test ******************
	
	;mov	 r1,#0x0  ;no change z flag
	;movs    r1,#0x0  ;change Z flag
	
	;***********************************
	
    ldr	    r0,=INTMSK
    ldr	    r1,=0x07ffffff  ;all interrupt disable
    str	    r1,[r0]

;************************************************************************************************************************    
;
;		Set clock control registers		
;
;************************************************************************************************************************    
    
    ldr	r0,=LOCKTIME		; PLL lock time count register
    ldr	r1,=1260	    		; count = t_lock * Fin (t_lock=210us, Fin=6MHz) = 1260
    str	r1,[r0]
    
	ldr	r0,=PLLCON			;temporary setting of PLL
	ldr	r1,=((0xe8<<12)+(0x4<<4)+0x2)	;Fin=4MHz,Fvco=160Mhz,Fout=40MHz,m/p/s=0x48/0/0x2
	str	r1,[r0]				; Fpllo = (m * Fin) / (p * 2s), m = (MDIV + 8), p = (PDIV + 2), s = SDIV
   							; MDIV = Bit[19..12]		Main divider control
   							; PDIV = Bit[9..4]			Pre-divider control
   							; SDIV = Bit[1..0]			Post divider control

    ldr	    r0,=CLKCON		 
    ldr	    r1,=0x7ff8	    ;All unit block CLK enable	0x7FF8 =  111 1111 1111 1000
    str	    r1,[r0]			;								  Bit[14 ..............0]
    						;Bit[14]:	Controls MCLK into IIS block
    						;Bit[13]:	Controls MCLK into IIC block
    						;Bit[12]:	Controls MCLK into ADC block
    						;Bit[11]:	Controls MCLK into RTC control block.Even if this bit is cleared to 0, RTC timer is alive.
    						;Bit[10]:	Controls MCLK into GPIO block .Set to 1 to use interrupt requests by EINT[4:7]
    						;Bit[9]:	Controls MCLK into UART1 block
    						;Bit[8]:	Controls MCLK into UART0 block
    						;Bit[7]:	Controls MCLK into BDMA block
    						;Bit[6]:	Controls MCLK into LCDC block
    						;Bit[5]:	Controls MCLK into SIO block
    						;Bit[4]:	Controls MCLK into ZDMA block
    						;Bit[3]:	Controls MCLK into PWMTIMER block
    						;Bit[2]:	Enters IDLE mode. This bit can t be cleared automatically.
    						;Bit[1]:	SL_IDLE mode option. This bit can t be cleared automatically.
    						;Bit[0]:	Enters STOP mode. This bit can t be cleared automatically. 

;************************************************************************************************************************    
;
;		Set memory control registers			
;	
;************************************************************************************************************************    
    
    ldr	    r0,=SMRDATA
    ldmia   r0,{r1-r13}
    ldr	    r0,=0x01c80000  ;BWSCON Address
    stmia   r0,{r1-r13}

;************************************************************************************************************************    
;
;		init uart0
;
;************************************************************************************************************************    
    
    ldr		r0,=RUFCON0		;FIFO disable
    ldr 	r1,=0
    str		r1,[r0]
    
    ldr		r0,=RUMCON0
    ldr 	r1,=0
    str		r1,[r0]
    
    ldr		r0,=RULCON0    ;Normal,No parity,1 stop,8 bit
    ldr 	r1,=0x3
    str		r1,[r0] 
    
    ldr		r0,=RUCON0     ;rx=edge,tx=level,disable timeout int.,enable rx error int.,normal,interrupt or polling
    ldr 	r1,=0x245
    str		r1,[r0]
    
    
;************************************************************************************************************************    
;
;		Initialize stacks				
;
;************************************************************************************************************************    
    
    ldr     sp,=0x10001fff
    
    ldr r3, =0x01d20028 	; PCONE(Port E Control) address
	ldr r4, =0x4000			; 0100 0000 0000 0000
    str r4, [r3]			; PE8 = Bit[17..16]:00 = Reserved(ENDIAN) 	01 = Output 	10 = CODECLK 11 = Reserved
							;					PE8 can be used as ENDIAN only during the reset cycle.
    						; PE7 = Bit[15..14]:00 = Input 01 = Output 	10 = TOUT4 		11 = VD7
    						; PE6 = Bit[13..12]:00 = Input 01 = Output 	10 = TOUT3 		11 = VD6
    						; PE5 = Bit[11..10]:00 = Input 01 = Output 	10 = TOUT2 		11 = TCLK in
    						; PE4 = Bit[9..8]:	00 = Input 01 = Output 	10 = TOUT1 		11 = TCLK in
    						; PE3 = Bit[7..6]: 	00 = Input 01 = Output 	10 = TOUT0 		11 = Reserved
    						; PE2 = Bit[5..4]:	00 = Input 01 = Output 	10 = RxD0 		11 = Reserved
    						; PE1 = Bit[3..2]:	00 = Input 01 = Output 	10 = TxD0 		11 = Reserved
    						; PE0 = Bit[1..0]:	00 = Input 01 = Output	10 = Fpllo out 	11 = Fout out
    						
                       		; change pwm4 pin state
    ldr r3, =0x01d2002c		; PDATE(Port E Data) address
    ldr r4, =0xff
    str r4, [r3]
    
;************************************************************************************************************************    
;
; 		sdram test
;
;************************************************************************************************************************    
    
sdram					; display  r0 = test address  r5 = read data  r1,r2 = write data
    ldr   r0, =0x0c000000
    ldr   r1, =0x55555555
    ldr   r2, =0xaaaaaaaa
    
sdram0 
   
    str  r1,[r0] 
    ldr  r5,[r0]
    cmp  r5,r1
    bne  sdramout
    ;b sdram0
    
    str  r2, [r0]
    ldr  r5, [r0]
    cmp  r5,r2
    bne  sdramout     ;  above code test data line
    
sdram1   
    
    str  r0,[r0]  
    add  r0,r0,#4
    cmp  r0,#0x0e000000
    beq  sdram2   
    b 	 sdram1     		; write address to the same cell
    
sdram2 
	
    ldr r0 , =0x0c000000
    
sdram3
   
    ldr  r5,[r0]
    cmp  r5,r0
    bne  sdramout
    add  r0,r0,#4
    cmp  r0,#0x0e000000
    beq  sdramout 
    b sdram3		;read data and compare with address
sdramout

    b  .    		; display  r0 = test address  r5 = read data  r1,r2 = write data
    

;************************************************************************************************************************    
;
; 	norflash
;
;************************************************************************************************************************    
   
out
    ldr r3, =0x01d2002c
    ldr r4, =0x00
    str r4, [r3]
    b  . 
    
     
;************************************************************************************************************************    
;