📄 init_44b0.s.bak
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;Interrupt Control
INTPND EQU 0x01e00004
INTMOD EQU 0x01e00008
INTMSK EQU 0x01e0000c
I_ISPR EQU 0x01e00020
I_CMST EQU 0x01e0001c
;Watchdog timer
WTCON EQU 0x01d30000
;Clock Controller
PLLCON EQU 0x01d80000
CLKCON EQU 0x01d80004
LOCKTIME EQU 0x01d8000c
;Memory Controller
REFRESH EQU 0x01c80024
;porta controller
PCONA EQU 0x01d20000
PDATA EQU 0x1d200004
; UART
RULCON0 EQU 0x1d00000
RUCON0 EQU 0x1d00004
RUFCON0 EQU 0x1d00008
RUMCON0 EQU 0x1d0000c
RUTRSTAT0 EQU 0x1d00010
RUERSTAT0 EQU 0x1d00014
RUFSTAT0 EQU 0x1d00018
RUMSTAT0 EQU 0x1d0001C
RUBRDIV0 EQU 0x1d00028
AREA Init,CODE,READONLY
; IMPORT __use_no_semihosting_swi
ENTRY
b ResetHandler ;for debug
b HandlerUndef ;handlerUndef
b HandlerSWI ;SWI interrupt handler
b HandlerPabort ;handlerPAbort
b HandlerDabort ;handlerDAbort
b . ;handlerReserved
b HandlerIRQ
b HandlerFIQ
ResetHandler
ldr r0,=WTCON ;watch dog disable
ldr r1,=0x0
str r1,[r0]
ldr r0,=INTMSK
ldr r1,=0x07ffffff ;all interrupt disable
str r1,[r0]
;****************************************************
;* Set clock control registers *
;****************************************************
ldr r0,=LOCKTIME
ldr r1,=800 ; count = t_lock * Fin (t_lock=200us, Fin=4MHz) = 800
str r1,[r0]
ldr r0,=PLLCON ;temporary setting of PLL
ldr r1,=((0xe8<<12)+(0x4<<4)+0x2) ;Fin=4MHz,Fvco=160Mhz,Fout=40MHz,m/p/s=0x48/0/0x2
str r1,[r0]
ldr r0,=CLKCON
ldr r1,=0x7ff8 ;All unit block CLK enable
str r1,[r0]
;****************************************************
;* Set memory control registers *
;****************************************************
ldr r0,=SMRDATA
ldmia r0,{r1-r13}
ldr r0,=0x01c80000 ;BWSCON Address
stmia r0,{r1-r13}
;****************************************************
;init uart0
;****************************************************
ldr r0,=RUFCON0 ;FIFO disable
ldr r1,=0
str r1,[r0]
ldr r0,=RUMCON0
ldr r1,=0
str r1,[r0]
ldr r0,=RULCON0 ;Normal,No parity,1 stop,8 bit
ldr r1,=0x3
str r1,[r0]
ldr r0,=RUCON0 ;rx=edge,tx=level,disable timeout int.,enable rx error int.,normal,interrupt or polling
ldr r1,=0x245
str r1,[r0]
;****************************************************
;* Initialize stacks *
;****************************************************
ldr sp,=0x10001fff
ldr r3, =0x01d20028 ; pcone
ldr r4, =0x4000
str r4, [r3]
; change pwm4 pin state
ldr r3, =0x01d2002c
ldr r4, =0xff
str r4, [r3]
;**********************************************************
; sdram test
;**********************************************************
sdram ; display r0 = test address r5 = read data r1,r2 = write data
ldr r0, =0x0c000000
ldr r1, =0x55555555
ldr r2, =0xaaaaaaaa
sdram0
str r1,[r0]
ldr r5,[r0]
cmp r5,r1
bne sdramout
str r2, [r0]
ldr r5, [r0]
cmp r5,r2
bne sdramout ; above code test data line
sdram1
str r0,[r0]
add r0,r0,#4
cmp r0,#0x0e000000
beq sdram2
b sdram1 ; write address to the same cell
sdram2
ldr r0 , =0x0c000000
sdram3
ldr r5,[r0]
cmp r5,r0
bne sdramout
cmp r0,#0x0e000000
beq nvram
b sdram3 ;read data and compare with address
sdramout
b . ; display r0 = test address r5 = read data r1,r2 = write data
;********************************************************
; nvram test
;********************************************************
nvram
ldr r0, =PCONA
ldr r1, [r0]
bic r1, r1, #0x1
str r1, [r0] ;set port A0 mode
ldr r0, =0x06000000
ldr r1, =0x55
ldr r2, =0xaa
ldr r3, =PDATA
ldr r4, [r3]
nvram0
bic r4, r4, #0x1
str r4, [r3]
str r1, [r0]
ldr r5, [r0]
cmp r1, r5
bne nvramout ;write even
orr r4, r4,#0x1
str r4, [r3]
str r2, [r0]
ldr r5, [r0]
cmp r2, r5
bne nvramout ; write odd
add r0, r0, #2
ldr r6, =0x06008000
cmp r0 , r6
beq norflash
b nvram0
nvramout
b .
;************************************************************
; norflash
;************************************************************
norflash
out
ldr r3, =0x01d2002c
ldr r4, =0x00
str r4, [r3]
b .
;****************************************************************
; ASCII INVERT in DATA ADDRESS, OUT UART0 ASCII
;****************************************************************
uart0
stmfd r13!, {r10,r11,r12}
BWSCON_cfg EQU 0x11110002 ;Bank0=16bit BootRom(AT29LV160DB) :0x0
; ||||||-- Bank1=low 8bit D12 :0x4
; |||||--- Bank2=8bit NAND-Flash(KM29U128T):0x2
; ||||---- Bank3=16bit Expend :0x6
; |||----- Bank4=16bit Expend :0x8
; ||------ Bank5=16bit ISA :0xA
; |------- Bank6=16bit SDRAM :0xc
; -------- Bank7=16bit NoUsed
;**********MEMORY CONTROL PARAMETERS*******************************
;When MCLK=66MHz,1clk=0.0152us=15.2ns
;Bank 0 parameter for Monitor Rom
GBLS BDRAMTYPE
BDRAMTYPE SETS "SDRAM"
B0_Tacs EQU 0x0 ;0clk
B0_Tcos EQU 0x0 ;0clk
B0_Tacc EQU 0x6 ;10clk
B0_Tcoh EQU 0x0 ;0clk
B0_Tah EQU 0x0 ;0clk
B0_Tacp EQU 0x0 ;0clk
B0_PMC EQU 0x0 ;normal(1data)
;Bank 1 parameter for SRAM
B1_Tacs EQU 0x3 ;4clk
B1_Tcos EQU 0x3 ;4clk
B1_Tacc EQU 0x7 ;14clk
B1_Tcoh EQU 0x3 ;4clk
B1_Tah EQU 0x3 ;4clk
B1_Tacp EQU 0x3 ;6clk
B1_PMC EQU 0x0 ;normal(1data)
;Bank 2 parameter for KM29U128T
B2_Tacs EQU 0x1 ;4clk
B2_Tcos EQU 0x2 ;4clk
B2_Tacc EQU 0x7 ;14clk
B2_Tcoh EQU 0x2 ;4clk
B2_Tah EQU 0x2 ;4clk
B2_Tacp EQU 0x3 ;6clk
B2_PMC EQU 0x0 ;normal(1data)
;Bank 3 parameter for USBN9603
B3_Tacs EQU 0x1 ;(Address set-up before nGCSn)
B3_Tcos EQU 0x2;(Chip selection set-up nOE)
B3_Tacc EQU 0x7 ;14clk(Access cycle)
B3_Tcoh EQU 0x2;(Chip selection hold on nOE)
B3_Tah EQU 0x2;(Address holding time after nGCSn)
B3_Tacp EQU 0x3 ;(Page mode access cycle @ Page mode)
B3_PMC EQU 0x0 ;normal(1data)
;Bank 4 parameter for IDE
B4_Tacs EQU 0x3 ;4clk
B4_Tcos EQU 0x4 ;4clk
B4_Tacc EQU 0x6 ;12clk
B4_Tcoh EQU 0x3 ;4clk
B4_Tah EQU 0x3 ;4clk
B4_Tacp EQU 0x3 ;6clk
B4_PMC EQU 0x0 ;normal(1data)
;Bank 5 parameter
B5_Tacs EQU 0x3 ;4clk 0x3 ;4clk
B5_Tcos EQU 0x3 ;4clk
B5_Tacc EQU 0x7 ;14clk 0x7 ;14clk
B5_Tcoh EQU 0x3 ;4clk
B5_Tah EQU 0x3 ;4clk 0x3 ;4clk
B5_Tacp EQU 0 ;0x3 ;6clk
B5_PMC EQU 0x0 ;normal(1data)
;Bank 6(if SROM) parameter
;B6_Tacs EQU 0x3 ;4clk
;B6_Tcos EQU 0x3 ;4clk
;B6_Tacc EQU 0x7 ;14clk
;B6_Tcoh EQU 0x3 ;4clk
;B6_Tah EQU 0x3 ;4clk
;B6_Tacp EQU 0x3 ;6clk
;B6_PMC EQU 0x0 ;normal(1data)
;Bank 7(if SROM) parameter
;B7_Tacs EQU 0x3 ;4clk
;B7_Tcos EQU 0x3 ;4clk
;B7_Tacc EQU 0x7 ;14clk
;B7_Tcoh EQU 0x3 ;4clk
;B7_Tah EQU 0x3 ;4clk
;B7_Tacp EQU 0x3 ;6clk
;B7_PMC EQU 0x0 ;normal(1data)
;Bank 6 parameter
[ BDRAMTYPE="DRAM" ;MT=01(FP DRAM) or 10(EDO DRAM)
B6_MT EQU 0x2 ;EDO DRAM
B6_Trcd EQU 0x1 ;2clk
B6_Tcas EQU 0x1 ;2clk
B6_Tcp EQU 0x1 ;2clk
B6_CAN EQU 0x2 ;10bit
| ;"SDRAM" ;MT=11(SDRAM)
B6_MT EQU 0x3 ;SDRAM
B6_Trcd EQU 0x0 ;2clk
B6_SCAN EQU 0x1 ;9bit
]
;Bank 7 parameter
[ BDRAMTYPE="DRAM" ;MT=01(FP DRAM) or 10(EDO DRAM)
B7_MT EQU 0x2 ;EDO DRAM
B7_Trcd EQU 0x1 ;2clk
B7_Tcas EQU 0x1 ;2clk
B7_Tcp EQU 0x1 ;2clk
B7_CAN EQU 0x2 ;10bit
| ;"SDRAM" ;MT=11(SDRAM)
B7_MT EQU 0x3 ;SDRAM
B7_Trcd EQU 0x0 ;2clk
B7_SCAN EQU 0x0 ;8bit
]
;REFRESH parameter
REFEN EQU 0x1 ;Refresh enable
TREFMD EQU 0x0 ;CBR(CAS before RAS)/Auto refresh
Trp EQU 0x1 ;3clk
Trc EQU 0x1 ;5clk
Tchr EQU 0x2 ;3clk
REFCNT EQU 1425 ;1019 ;period=15.6us, MCLK=66Mhz
;************************************************
SMRDATA DATA
DCD BWSCON_cfg
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
[ BDRAMTYPE="DRAM"
DCD ((B6_MT<<15)+(B6_Trcd<<4)+(B6_Tcas<<3)+(B6_Tcp<<2)+(B6_CAN)) ;GCS6 check the MT value in parameter.a
DCD ((B7_MT<<15)+(B7_Trcd<<4)+(B7_Tcas<<3)+(B7_Tcp<<2)+(B7_CAN)) ;GCS7
| ;"SDRAM"
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7
]
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) ;REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019
DCD 0x10 ;SCLK power down mode, BANKSIZE 32M/32M
DCD 0x20 ;MRSR6 CL=2clk
DCD 0x20 ;MRSR7
HandlerUndef
b .
HandlerSWI
b .
HandlerPabort
b .
HandlerDabort
b .
HandlerIRQ
b .
HandlerFIQ
b .
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