📄 main_edma1.c.bak
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/********************************************************************************/
/* b_perph.c */
/* written by David Bell */
/* on 01/09/01 */
/* */
/* b_perph uses a single EDMA channel to service an external AFE. Channel 4 is */
/* used to burst a frame of data for every EXT_INT4 event received. The data is */
/* transferred from the AFE to L2 memory. */
/********************************************************************************/
#define CHIP_6713 1
#include <stdio.h>
#include <csl_cache.h>
#include <csl_timer.h>
#include <csl_irq.h>
#include <csl.h>
#include <csl_edma.h>
#include <c6x.h>
#include "c6211dsk.h"
#include "math.h"
/* definitions */
#define MEM_SRC 0x8000 /* Source address for transfer */
#define MEM_DST 0xB0280000 /* Switch(2..0) = 001 0xB0000000 Switch(2..0) =000 */
#define EL_COUNT 2049 /* Element count for transfer */
#define FR_COUNT 1
#define pi 3.14159265
/* PLL configuration */
#define PLL_DIV0 0
#define PLL_DIV1 1
#define PLL_DIV2 2
#define PLL_DIV3 3
int w;
int sin_table[80]={
0x0000,
0x0063,
0x0184,
0x0347,
0x057F,
0x07F5,
0x0A6A,
0x0CA2,
0x0E65,
0x0F87,
0x0FEB,
0x0F88,
0x0E66,
0x0CA4,
0x0A6C,
0x07F6,
0x0581,
0x0348,
0x0185,
0x0064,
0x0000,
0x0063,
0x0184,
0x0347,
0x057F,
0x07F4,
0x0A6A,
0x0CA2,
0x0E65,
0x0F87,
0x0FEB,
0x0F88,
0x0E67,
0x0CA4,
0x0A6C,
0x07F7,
0x0581,
0x0349,
0x0185,
0x0064,
0x0000,
0x0063,
0x0184,
0x0347,
0x057F,
0x07F5,
0x0A6A,
0x0CA2,
0x0E65,
0x0F87,
0x0FEB,
0x0F88,
0x0E66,
0x0CA4,
0x0A6C,
0x07F6,
0x0581,
0x0348,
0x0185,
0x0064,
0x0000,
0x0063,
0x0184,
0x0347,
0x057F,
0x07F5,
0x0A6A,
0x0CA2,
0x0E65,
0x0F87,
0x0FEB,
0x0F88,
0x0E66,
0x0CA4,
0x0A6C,
0x07F6,
0x0581,
0x0348,
0x0185,
0x0064
};
/* prototypes */
void submit_qdmas(void);
void submit_qdma(void);
void wait(void);
void startPLL();
void delay();
extern far void vectors();
void setupInterrupts(void);
/***********************************submit_qdma**********************************/
/* Submit a QDMA request to transfer the data. */
/********************************************************************************/
void
submit_qdma(void)
{
EDMA_Config config;
config.opt = (Uint32) /* 0x21200001 */
((EDMA_OPT_PRI_HIGH << _EDMA_OPT_PRI_SHIFT )
| (EDMA_OPT_ESIZE_32BIT << _EDMA_OPT_ESIZE_SHIFT )
| (EDMA_OPT_2DS_NO << _EDMA_OPT_2DS_SHIFT )
| (EDMA_OPT_SUM_INC << _EDMA_OPT_SUM_SHIFT )
| (EDMA_OPT_2DD_NO << _EDMA_OPT_2DD_SHIFT )
| (EDMA_OPT_DUM_NONE << _EDMA_OPT_DUM_SHIFT )
| (EDMA_OPT_TCINT_NO << _EDMA_OPT_TCINT_SHIFT )
| (EDMA_OPT_TCC_DEFAULT << _EDMA_OPT_TCC_SHIFT )
#if (C64_SUPPORT)
| (EDMA_OPT_TCCM_DEFAULT << _EDMA_OPT_TCCM_SHIFT )
| (EDMA_OPT_ATCINT_NO << _EDMA_OPT_ATCINT_SHIFT)
| (EDMA_OPT_ATCC_DEFAULT << _EDMA_OPT_ATCC_SHIFT )
| (EDMA_OPT_PDTS_DISABLE << _EDMA_OPT_PDTS_SHIFT )
| (EDMA_OPT_PDTD_DISABLE << _EDMA_OPT_PDTD_SHIFT )
#endif
| (EDMA_OPT_LINK_NO << _EDMA_OPT_LINK_SHIFT )
| (EDMA_OPT_FS_YES << _EDMA_OPT_FS_SHIFT ));
config.src = (unsigned int)MEM_SRC; /* 0x80000000 */
config.cnt = (unsigned int)EL_COUNT; /* 0x00000100 */
config.dst = (unsigned int)MEM_DST; /* 0x00002000 */
config.idx = (unsigned int)0; /* 0x00000000 */
EDMA_qdmaConfig(&config);
} /* end submit_qdma */
/**************************************wait**************************************/
/* Wait until the transfer completes, as indicated by the status of the low- */
/* priority queue in the queue status register (QSR). */
/********************************************************************************/
void
wait(void)
{
while (!(EDMA_getPriQStatus() & EDMA_OPT_PRI_HIGH));
} /* end wait */
/**************************************main**************************************/
/* Main code body. */
/********************************************************************************/
void
main(void)
{
int m,a,b,x,y,i,n,qw;
int k=0xfff;
//float w=0.0;
int data=0x0;
int re[50] = 0x0000;
float mid[50];
for(i=0;i++;i<50)
{
mid[i] = 2048*(sin(pi*i/25)+1);
qw=3;
}
for(i=0;i++;i<50)
{
re[i] = (int)mid[i];
qw=5;
}
/* for(i=0;i++;i<50)
{
mid = (sin(2*pi*i/50)+1)*2047;
result[i] = (int)mid ;
}
*/
/* DSP initialization */
CSR=0x100; /* Disable all interrupts */
IER=1; /* Disable all interrupts except NMI */
ICR=0xffff; /* Clear all pending interrupts */
// PLL Configuration
startPLL();
delay();
*(unsigned volatile int *)EMIF_GCR = 0x3778;
*(unsigned volatile int *)EMIF_CE0 = 0x30; /* EMIF CE1 control, 32bit */
*(unsigned volatile int *)EMIF_CE1 = CE1_8; /* EMIF CE1 control, 32bit */
*(unsigned volatile int *)EMIF_CE2 = 0x30; /* EMIF CE1 control, 32bit */
*(unsigned volatile int *)EMIF_CE3 = CE1_32; /* EMIF CE1 control, 32bit */
*(unsigned volatile int *)EMIF_SDCTRL = 0x07126000; /* EMIF SDRAM control */
*(unsigned volatile int *)EMIF_SDRP = 0x61a; /* EMIF SDRM refresh period */
*(unsigned volatile int *)EMIF_SDEXT= 0x54529; /* EMIF SDRM extension */
/* Configure L2 for 64K Cache and enable caching of external memory*/
for(i=0;i<5;i++)
{
*(short int *)(0xB0040000) = 0x000;
}
for(i=0;i<5;i++)
{
*(short int *)(0xB0040000) = 0x001;
}
/*
for(i=0;i<160;i++)
{
// w = (4096*sin(8*3.1415*i/160)+4096)/2.01;
//a = ( int )w;
*( int *)(0x30000+4*i) = sin_table[i];
// *( int *)(0x30000+4*i) = a;
}
*/
for(n=0;n<100;n++)
{
for(i=0;i<40;i++)
{
a =*(int *)(0x30000+4*i);
x =*(int *)(0x30000+20+4*i);
b =(x<<16)+a;
*( int *)(0x8000+4*i+160*n)=b;
}
i=0;
}
submit_qdma();
wait();
i=0;
submit_qdma();
wait();
i=0;
for(i=0;i<5;i++)
{
*(short int *)(0xB0040000) = 0x000;
}
for(i=0;i<5;i++)
{
*(short int *)(0xB0040000) = 0xFFFFFFFF;
*(short int *)(0xB004000C) = 0xFFFFFFFF;
*(short int *)(0xB0040010) = 0xFFFFFFFF;
}
IRQ_setVecs(vectors);
IRQ_globalEnable();
IRQ_nmiEnable();
IRQ_map(IRQ_EVT_EXTINT4, 4);
IRQ_reset(IRQ_EVT_EXTINT4);
IRQ_enable(IRQ_EVT_EXTINT4);
IER =0;
w=0x3;
//for(;;)
{
data = w;
// start bit
for(i=0;i<20;i++)
{
*( int *)(0x30000+4*i+80*0) = 2047;
}
for(i=0;i<20;i++)
{
*( int *)(0x30000+4*i+80*1) = 2047;
}
for(i=0;i<20;i++)
{
*( int *)(0x30000+4*i+80*2) = 2047;
}
for(i=0;i<20;i++)
{
*( int *)(0x30000+4*i+80*3) = 2047;
}
//data
for(i=0;i<40;i++)
{
*( int *)(0x30000+4*i+80*4) = sin_table[i*(1+(data&0x01))];
}
for(i=0;i<40;i++)
{
*( int *)(0x30000+4*i+80*5+80) = sin_table[i*(1+((data&0x02)>>1))];
}
for(i=0;i<40;i++)
{
*( int *)(0x30000+4*i+80*6+160) = sin_table[i*(1+((data&0x04)>>2))];
}
for(i=0;i<40;i++)
{
*( int *)(0x30000+4*i+80*7+240) = sin_table[i*(1+((data&0x08)>>3))];
}
// end data
for(n=0;n<32;n++)
{
for(i=0;i<960;i++)
{
a =*(int *)(0x30000+4*i);
x =*(int *)(0x30000+20+4*i);
b =(x<<16)+a;
*( int *)(0x8000+4*i+960*n)=b;
}
i=0;
}
for(n=0;n<0xffff;n++)
{
submit_qdma();
wait();
}
for(;;)
i=0;
}
} /* end main */
/******************************************************************************\
* PLL initial Programm
\******************************************************************************/
void startPLL()
{
PLL_bypass();
delay();
PLL_reset();
delay();
PLL_setPllRatio(PLL_DIV0,0x1); /* DIVD0 Ndiv */ //clock_in = 40MHz
PLL_enablePllDiv(PLL_DIV0);
PLL_setMultiplier(20); /* Mmul Multiply by the number */
// system_clock=(clock_in/Ndiv)* Mmul
// system_clock=(40/1)*5=200MHz
PLL_setOscRatio(0x0); // clock out3
PLL_enableOscDiv();
delay();
// PLL_operational();
PLL_setPllRatio(PLL_DIV1,0x1); // system_clk1 for DSP core
// DSPcore = system_clock/1 = 200MHz
PLL_enablePllDiv(PLL_DIV1); /* dsp core divide bu the number+1*/
delay();
PLL_setPllRatio(PLL_DIV2,0x09); /* peripheral sysclk2 divide by the number+1*/
PLL_enablePllDiv(PLL_DIV2); // Peripherals R62 测量
// peripheral sysclk2 = system_clock/(9+1) = 20MHz
delay();
PLL_setPllRatio(PLL_DIV3,0x4); /* sysclk3 divide bu the number+1*/
PLL_enablePllDiv(PLL_DIV3); // EMIF interface clock
// EMIF sysclk = 200/2 =100MHz
delay();
delay();
PLL_deassert();
delay();
delay();
PLL_enable();
delay();
delay();
return;
}
void delay()
{
int i;
for(i=0;i<0xfff;i++){}
return;
}
/************************************************************************\
name: SetInterruptsEdma
purpose: Sets up interrupts to service EDMA transfers
inputs: void
returns: void
\************************************************************************/
void setupInterrupts(void)
{
IRQ_setVecs(vectors); /* point to the IRQ vector table */
IRQ_nmiEnable();
IRQ_globalEnable();
IRQ_map(IRQ_EVT_EXTINT4, 4);
IRQ_reset(IRQ_EVT_EXTINT4);
} /* End of SetInterruptsEdma() */
/************************************************************************\
name: Interrupt Service Routine c_int04
\************************************************************************/
interrupt void
c_int04(void)
{
int i;
IER = 0;
IRQ_clear(IRQ_EVT_EXTINT4);
submit_qdma();
w=!w;
//*(short int *)(0x90080000) = w;
// wait();
IRQ_enable(IRQ_EVT_EXTINT4);
return;
}⌨️ 快捷键说明
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