ad0809.map.qmsg

来自「非常好的原代码」· QMSG 代码 · 共 61 行 · 第 1/5 页

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1\|holdff data_in VCC " "Warning: Reduced register \"sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1\|holdff\" with stuck data_in port to stuck value VCC" {  } { { "sld_mbpmg.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 309 -1 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[2\] High " "Info: Power-up level of register \"sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[2\]\" is not specified -- using power-up level of High to minimize register" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[2\] data_in VCC " "Warning: Reduced register \"sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[2\]\" with stuck data_in port to stuck value VCC" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1\|holdff High " "Info: Power-up level of register \"sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1\|holdff\" is not specified -- using power-up level of High to minimize register" {  } { { "sld_mbpmg.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 309 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1\|holdff data_in VCC " "Warning: Reduced register \"sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1\|holdff\" with stuck data_in port to stuck value VCC" {  } { { "sld_mbpmg.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 309 -1 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "sld_signaltap:auto_signaltap_0\|acq_data_in_reg\[0\] High " "Info: Power-up level of register \"sld_signaltap:auto_signaltap_0\|acq_data_in_reg\[0\]\" is not specified -- using power-up level of High to minimize register" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|acq_data_in_reg\[0\] data_in VCC " "Warning: Reduced register \"sld_signaltap:auto_signaltap_0\|acq_data_in_reg\[0\]\" with stuck data_in port to stuck value VCC" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "sld_signaltap:auto_signaltap_0\|acq_data_in_reg\[1\] High " "Info: Power-up level of register \"sld_signaltap:auto_signaltap_0\|acq_data_in_reg\[1\]\" is not specified -- using power-up level of High to minimize register" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|acq_data_in_reg\[1\] data_in VCC " "Warning: Reduced register \"sld_signaltap:auto_signaltap_0\|acq_data_in_reg\[1\]\" with stuck data_in port to stuck value VCC" {  } { { "sld_