ax88796.c

国外牛人公开的ＡＶＲ代码

	// clear the packet received interrupt flag
	ax88796Write(ISR, PRX);
	
	// if the boundary pointer is invalid,
	// reset the contents of the buffer and exit
	if( (bnryPagePtr < RXSTART_INIT) || (bnryPagePtr >= RXSTOP_INIT) )
	{
		ax88796Write(BNRY, RXSTART_INIT);
		ax88796Write(CR, (PS0|RD2|START));
		ax88796Write(CURR, RXSTART_INIT+1);
		ax88796Write(CR, (RD2|START));
		
//		rprintf("B");
		return 0;
	}

	// initiate DMA to transfer the RTL8019 packet header
	ax88796Write(RBCR0, 4);
	ax88796Write(RBCR1, 0);
	ax88796Write(RSAR0, 0);
	ax88796Write(RSAR1, readPagePtr);
	ax88796Write(CR, (RD0|START));
	for(i=0;i<4;i++)
		pageheader[i] = ax88796Read(RDMAPORT);

	// end the DMA operation
    ax88796Write(CR, (RD2|START));
    for(i = 0; i <= 20; i++)
        if(ax88796Read(ISR) & RDC)
            break;
    ax88796Write(ISR, RDC);
	
	rxlen = (pageheader[PKTHEADER_PKTLENH]<<8) + pageheader[PKTHEADER_PKTLENL];
	NextPage = pageheader[PKTHEADER_NEXTPAGE];
	
	CurrentRetreiveAddress = (readPagePtr<<8) + 4;
	
	// if the NextPage pointer is invalid, the packet is not ready yet - exit
	if( (NextPage >= RXSTOP_INIT) || (NextPage < RXSTART_INIT) )
	{
//		rprintf("N");
//		rprintfu08(nextPage);
		return 0;
	}

    return rxlen-4;
}


void ax88796RetreivePacketData(unsigned char * localBuffer, unsigned int length)
{
	unsigned int i;
	
	// initiate DMA to transfer the data
	ax88796Write(RBCR0, (unsigned char)length);
	ax88796Write(RBCR1, (unsigned char)(length>>8));
	ax88796Write(RSAR0, (unsigned char)CurrentRetreiveAddress);
	ax88796Write(RSAR1, (unsigned char)(CurrentRetreiveAddress>>8));
	ax88796Write(CR, (RD0|START));
	for(i=0;i<length;i++)
		localBuffer[i] = ax88796Read(RDMAPORT);

	// end the DMA operation
	ax88796Write(CR, (RD2|START));
	for(i = 0; i <= 20; i++)
		if(ax88796Read(ISR) & RDC)
			break;
	ax88796Write(ISR, RDC);
    
	CurrentRetreiveAddress += length;
	if( CurrentRetreiveAddress >= 0x6000 )
    	CurrentRetreiveAddress -= (0x6000-0x4600) ;
}


void ax88796EndPacketRetreive(void)
{
	unsigned char i;
	unsigned char bnryPagePtr;

	// end the DMA operation
    ax88796Write(CR, (RD2|START));
    for(i = 0; i <= 20; i++)
        if(ax88796Read(ISR) & RDC)
            break;
    ax88796Write(ISR, RDC);

	// set the boundary register to point
	// to the start of the next packet-1
    bnryPagePtr = NextPage-1;
	if(bnryPagePtr < RXSTART_INIT) bnryPagePtr = RXSTOP_INIT-1;

	ax88796Write(BNRY, bnryPagePtr);
}


void ax88796ProcessInterrupt(void)
{
	unsigned char intr = ax88796Read(ISR);
	
	// check for receive overflow
	if( intr & OVW )
		ax88796ReceiveOverflowRecover();
}


void ax88796ReceiveOverflowRecover(void)
{
	// receive buffer overflow handling procedure
	// as specified in the AX88796 datasheet

	unsigned char cmdReg;
	unsigned char resend=0;

	// check if we were transmitting something
	cmdReg = ax88796Read(CR);
	// stop the interface
	ax88796Write(CR, (RD2|STOP));
	// wait for timeout
	delay_ms(2);
	// clear remote byte count registers
	ax88796Write(RBCR0, 0x00);
	ax88796Write(RBCR1, 0x00);
	
	// if we were transmitting something
	if(cmdReg & TXP)
	{
		// check if the transmit completed
		cmdReg = ax88796Read(ISR);
		if((cmdReg & PTX) || (cmdReg & TXE))
			resend = 0;		// transmit completed
	    else
			resend = 1;		// transmit was interrupted, must resend
	}
	// switch to loopback mode
	ax88796Write(TCR, LB0);
	// start the interface
	ax88796Write(CR, (RD2|START));
	// set boundary
	ax88796Write(BNRY, RXSTART_INIT);
	// go to page 1
	ax88796Write(CR, (PS0|RD2|START));
	// set current page register
	ax88796Write(CPR, RXSTART_INIT+1);
	// go to page 0
	ax88796Write(CR, (RD2|START));
	// clear the overflow int
	ax88796Write(ISR, OVW);
	// switch to normal (non-loopback mode)
	ax88796Write(TCR, TCR_INIT);

	// if previous transmit was interrupted, then resend
	if(resend)
		ax88796Write(CR, (RD2|TXP|START));

	// recovery completed
}


#define set_mdc		ax88796Write(MEMR,ax88796Read(MEMR)|0x01);
#define clr_mdc		ax88796Write(MEMR,ax88796Read(MEMR)&0xFE);

#define mii_clk		set_mdc; clr_mdc;				  
					
#define set_mdir	ax88796Write(MEMR,ax88796Read(MEMR)|0x02);
#define clr_mdir	ax88796Write(MEMR,ax88796Read(MEMR)&0xFD);
					
#define set_mdo		ax88796Write(MEMR,ax88796Read(MEMR)|0x08)
#define clr_mdo		ax88796Write(MEMR,ax88796Read(MEMR)&0xF7)

#define mii_write	clr_mdo; mii_clk;	\
					set_mdo; mii_clk;	\
					clr_mdo; mii_clk;	\
					set_mdo; mii_clk;

#define mii_read	clr_mdo; mii_clk;	\
					set_mdo; mii_clk;	\
					set_mdo; mii_clk;	\
					clr_mdo; mii_clk;

#define mii_r_ta    mii_clk;			\

#define mii_w_ta    set_mdo; mii_clk;	\
					clr_mdo; mii_clk;
			
void ax88796WriteMii(unsigned char phyad,unsigned char regad,unsigned int mii_data)
{
	unsigned char mask8;
	unsigned int  i,mask16;

	mii_write;
 
	mask8 = 0x10;
	for(i=0;i<5;++i)
	{
  	   	if(mask8 & phyad)
			set_mdo;
		else
			clr_mdo;
		mii_clk;
		mask8 >>= 1;	 
	}   
	mask8 = 0x10;
	for(i=0;i<5;++i)
	{
  		if(mask8 & regad)
			set_mdo;
		else
			clr_mdo;
		mii_clk;
		mask8 >>= 1;	 
	}    					
	mii_w_ta;
 
	mask16 = 0x8000;
	for(i=0;i<16;++i)
	{
		if(mask16 & mii_data)
			set_mdo;
		else
			clr_mdo;
		mii_clk;	 
		mask16 >>= 1;	 
	}   			
}
 
unsigned int ax88796ReadMii(unsigned char phyad,unsigned char regad)
{
	unsigned char mask8,i;
	unsigned int  mask16,result16;
 
	mii_read;

	mask8 = 0x10;
	for(i=0;i<5;++i)
	{
		if(mask8 & phyad)
			set_mdo;
		else
			clr_mdo;
		mii_clk;	 
		mask8 >>= 1;
	}
	mask8 = 0x10;
	for(i=0;i<5;++i)
	{
		if(mask8 & regad)
			set_mdo;
		else
			clr_mdo;
		mii_clk;
		mask8 >>= 1;
	}
   			
	mii_r_ta;
 
	mask16 = 0x8000;
	result16 = 0x0000;
	for(i=0;i<16;++i)
	{
		mii_clk;
		if(ax88796Read(MEMR) & 0x04)
		{
			result16 |= mask16;
		}
		else
		{
			asm volatile ("nop");
			break;
		}
		mask16 >>= 1;
	}
	return result16;
}


void ax88796RegDump(void)
{
	unsigned char result;
	result = ax88796Read(TR);
	
	rprintf("Media State: ");
	if(!(result & AUTOD))
   		rprintf("Autonegotiation\r\n");
	else if(result & RST_B)
   		rprintf("PHY in Reset   \r\n");
	else if(!(result & RST_10B))
		rprintf("10BASE-T       \r\n");
	else if(!(result & RST_TXB))
		rprintf("100BASE-T      \r\n");
				
	//rprintf("TR regsiter      : %x\r\n",result);
	//result = read_mii(0x10,0);
	//rprintf("MII regsiter 0x10: %x\r\n",result);

	rprintfProgStrM("Page0: CR  BNRY PSR PST ISR TSR RSR MMR TR  GPI\r\n");
	rprintfProgStrM("       ");
	rprintfu08(ax88796Read(CR));
	rprintfProgStrM("  ");
	rprintfu08(ax88796Read(BNRY));
	rprintfProgStrM("   ");
	rprintfu08(ax88796Read(PSTART));
	rprintfProgStrM("  ");
	rprintfu08(ax88796Read(PSTOP));
	rprintfProgStrM("  ");
	rprintfu08(ax88796Read(ISR));
	rprintfProgStrM("  ");
	rprintfu08(ax88796Read(TSR));
	rprintfProgStrM("  ");
	rprintfu08(ax88796Read(RSR));
	rprintfProgStrM("  ");
	rprintfu08(ax88796Read(MEMR));
	rprintfProgStrM("  ");
	rprintfu08(ax88796Read(TR));
	rprintfProgStrM("  ");
	rprintfu08(ax88796Read(GPI));
	rprintfCRLF();

	ax88796Write(CR,ax88796Read(CR)|PS0);

	rprintf("Page1: CR  PAR    CPR\r\n");
	rprintfProgStrM("       ");
	rprintfu08(ax88796Read(CR));
	rprintfProgStrM("  ");
	rprintfChar(ax88796Read(PAR0));
	rprintfChar(ax88796Read(PAR1));
	rprintfChar(ax88796Read(PAR2));
	rprintfChar(ax88796Read(PAR3));
	rprintfChar(ax88796Read(PAR4));
	rprintfChar(ax88796Read(PAR5));
	rprintfProgStrM(" ");
	rprintfu08(ax88796Read(CPR));
	
	ax88796Write(CR,ax88796Read(CR)&~PS0);

	delay_ms(25);
}

/*
unsigned char ax88796ReceiveEmpty(void)
{
	unsigned char temp;

	// read CPR from page 1
	ax88796Write(CR,0x62);
	temp = ax88796Read(CPR);
	
	// return to page 0
	ax88796Write(CR,0x22);
	
	return ( ax88796Read(BNRY) == temp );
	
}*/