enc28j60_8c-source.html

国外牛人公开的ＡＶＲ代码

00173     <span class="comment">// issue write command</span>
00174     SPDR = ENC28J60_WRITE_BUF_MEM;
00175     <span class="keywordflow">while</span>(!(SPSR &amp; (1&lt;&lt;SPIF)));
00176     <span class="keywordflow">while</span>(len--)
00177     {
00178         <span class="comment">// write data</span>
00179         SPDR = *data++;
00180         <span class="keywordflow">while</span>(!(SPSR &amp; (1&lt;&lt;SPIF)));
00181     }   
00182     <span class="comment">// release CS</span>
00183     ENC28J60_CONTROL_PORT |= (1&lt;&lt;ENC28J60_CONTROL_CS);
00184 }
00185 
<a name="l00186"></a><a class="code" href="group__enc28j60.html#ga4">00186</a> <span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga4">enc28j60SetBank</a>(u08 address)
00187 {
00188     <span class="comment">// set the bank (if needed)</span>
00189     <span class="keywordflow">if</span>((address &amp; BANK_MASK) != Enc28j60Bank)
00190     {
00191         <span class="comment">// set the bank</span>
00192         <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_BIT_FIELD_CLR, ECON1, (ECON1_BSEL1|ECON1_BSEL0));
00193         <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_BIT_FIELD_SET, ECON1, (address &amp; BANK_MASK)&gt;&gt;5);
00194         Enc28j60Bank = (address &amp; BANK_MASK);
00195     }
00196 }
00197 
<a name="l00198"></a><a class="code" href="group__enc28j60.html#ga5">00198</a> u08 <a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(u08 address)
00199 {
00200     <span class="comment">// set the bank</span>
00201     <a class="code" href="group__enc28j60.html#ga4">enc28j60SetBank</a>(address);
00202     <span class="comment">// do the read</span>
00203     <span class="keywordflow">return</span> <a class="code" href="group__enc28j60.html#ga0">enc28j60ReadOp</a>(ENC28J60_READ_CTRL_REG, address);
00204 }
00205 
<a name="l00206"></a><a class="code" href="group__enc28j60.html#ga6">00206</a> <span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(u08 address, u08 data)
00207 {
00208     <span class="comment">// set the bank</span>
00209     <a class="code" href="group__enc28j60.html#ga4">enc28j60SetBank</a>(address);
00210     <span class="comment">// do the write</span>
00211     <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_WRITE_CTRL_REG, address, data);
00212 }
00213 
<a name="l00214"></a><a class="code" href="group__enc28j60.html#ga7">00214</a> u16 <a class="code" href="group__enc28j60.html#ga7">enc28j60PhyRead</a>(u08 address)
00215 {
00216     u16 data;
00217 
00218     <span class="comment">// Set the right address and start the register read operation</span>
00219     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MIREGADR, address);
00220     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MICMD, MICMD_MIIRD);
00221 
00222     <span class="comment">// wait until the PHY read completes</span>
00223     <span class="keywordflow">while</span>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MISTAT) &amp; MISTAT_BUSY);
00224 
00225     <span class="comment">// quit reading</span>
00226     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MICMD, 0x00);
00227     
00228     <span class="comment">// get data value</span>
00229     data  = <a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MIRDL);
00230     data |= <a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MIRDH);
00231     <span class="comment">// return the data</span>
00232     <span class="keywordflow">return</span> data;
00233 }
00234 
<a name="l00235"></a><a class="code" href="group__enc28j60.html#ga8">00235</a> <span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga8">enc28j60PhyWrite</a>(u08 address, u16 data)
00236 {
00237     <span class="comment">// set the PHY register address</span>
00238     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MIREGADR, address);
00239     
00240     <span class="comment">// write the PHY data</span>
00241     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MIWRL, data); 
00242     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MIWRH, data&gt;&gt;8);
00243 
00244     <span class="comment">// wait until the PHY write completes</span>
00245     <span class="keywordflow">while</span>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MISTAT) &amp; MISTAT_BUSY);
00246 }
00247 
<a name="l00248"></a><a class="code" href="group__enc28j60.html#ga9">00248</a> <span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga9">enc28j60Init</a>(<span class="keywordtype">void</span>)
00249 {
00250     <span class="comment">// initialize I/O</span>
00251     sbi(ENC28J60_CONTROL_DDR, ENC28J60_CONTROL_CS);
00252     sbi(ENC28J60_CONTROL_PORT, ENC28J60_CONTROL_CS);
00253 
00254     <span class="comment">// setup SPI I/O pins</span>
00255     sbi(PORTB, 1);  <span class="comment">// set SCK hi</span>
00256     sbi(DDRB, 1);   <span class="comment">// set SCK as output</span>
00257     cbi(DDRB, 3);   <span class="comment">// set MISO as input</span>
00258     sbi(DDRB, 2);   <span class="comment">// set MOSI as output</span>
00259     sbi(DDRB, 0);   <span class="comment">// SS must be output for Master mode to work</span>
00260     <span class="comment">// initialize SPI interface</span>
00261     <span class="comment">// master mode</span>
00262     sbi(SPCR, MSTR);
00263     <span class="comment">// select clock phase positive-going in middle of data</span>
00264     cbi(SPCR, CPOL);
00265     <span class="comment">// Data order MSB first</span>
00266     cbi(SPCR,DORD);
00267     <span class="comment">// switch to f/4 2X = f/2 bitrate</span>
00268     cbi(SPCR, SPR0);
00269     cbi(SPCR, SPR1);
00270     sbi(SPSR, SPI2X);
00271     <span class="comment">// enable SPI</span>
00272     sbi(SPCR, SPE);
00273 
00274     <span class="comment">// perform system reset</span>
00275     <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
00276     <span class="comment">// check CLKRDY bit to see if reset is complete</span>
00277     delay_us(50);
00278     <span class="keywordflow">while</span>(!(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(ESTAT) &amp; ESTAT_CLKRDY));
00279 
00280     <span class="comment">// do bank 0 stuff</span>
00281     <span class="comment">// initialize receive buffer</span>
00282     <span class="comment">// 16-bit transfers, must write low byte first</span>
00283     <span class="comment">// set receive buffer start address</span>
00284     NextPacketPtr = RXSTART_INIT;
00285     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ERXSTL, RXSTART_INIT&amp;0xFF);
00286     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ERXSTH, RXSTART_INIT&gt;&gt;8);
00287     <span class="comment">// set receive pointer address</span>
00288     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ERXRDPTL, RXSTART_INIT&amp;0xFF);
00289     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ERXRDPTH, RXSTART_INIT&gt;&gt;8);
00290     <span class="comment">// set receive buffer end</span>
00291     <span class="comment">// ERXND defaults to 0x1FFF (end of ram)</span>
00292     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ERXNDL, RXSTOP_INIT&amp;0xFF);
00293     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ERXNDH, RXSTOP_INIT&gt;&gt;8);
00294     <span class="comment">// set transmit buffer start</span>
00295     <span class="comment">// ETXST defaults to 0x0000 (beginnging of ram)</span>
00296     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ETXSTL, TXSTART_INIT&amp;0xFF);
00297     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ETXSTH, TXSTART_INIT&gt;&gt;8);
00298 
00299     <span class="comment">// do bank 2 stuff</span>
00300     <span class="comment">// enable MAC receive</span>
00301     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MACON1, MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS);
00302     <span class="comment">// bring MAC out of reset</span>
00303     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MACON2, 0x00);
00304     <span class="comment">// enable automatic padding and CRC operations</span>
00305     <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);
00306 <span class="comment">//  enc28j60Write(MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);</span>
00307     <span class="comment">// set inter-frame gap (non-back-to-back)</span>
00308     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAIPGL, 0x12);
00309     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAIPGH, 0x0C);
00310     <span class="comment">// set inter-frame gap (back-to-back)</span>
00311     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MABBIPG, 0x12);
00312     <span class="comment">// Set the maximum packet size which the controller will accept</span>
00313     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAMXFLL, MAX_FRAMELEN&amp;0xFF);  
00314     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAMXFLH, MAX_FRAMELEN&gt;&gt;8);
00315 
00316     <span class="comment">// do bank 3 stuff</span>
00317     <span class="comment">// write MAC address</span>
00318     <span class="comment">// NOTE: MAC address in ENC28J60 is byte-backward</span>
00319     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR5, ENC28J60_MAC0);
00320     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR4, ENC28J60_MAC1);
00321     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR3, ENC28J60_MAC2);
00322     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR2, ENC28J60_MAC3);
00323     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR1, ENC28J60_MAC4);
00324     <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR0, ENC28J60_MAC5);
00325 
00326     <span class="comment">// no loopback of transmitted frames</span>
00327     <a class="code" href="group__enc28j60.html#ga8">enc28j60PhyWrite</a>(PHCON2, PHCON2_HDLDIS);
00328 
00329     <span class="comment">// switch to bank 0</span>
00330     <a class="code" href="group__enc28j60.html#ga4">enc28j60SetBank</a>(ECON1);
00331     <span class="comment">// enable interrutps</span>
00332     <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE);
00333     <span class="comment">// enable packet reception</span>
00334     <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
00335 <span class="comment">/*</span>
00336 <span class="comment">    enc28j60PhyWrite(PHLCON, 0x0AA2);</span>
00337 <span class="comment"></span>
00338 <span class="comment">    // setup duplex ----------------------</span>
00339 <span class="comment"></span>
00340 <span class="comment">    // Disable receive logic and abort any packets currently being transmitted</span>
00341 <span class="comment">    enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS|ECON1_RXEN);</span>
00342 <span class="comment">    </span>
00343 <span class="comment">    {</span>
00344 <span class="comment">        u16 temp;</span>
00345 <span class="comment">        // Set the PHY to the proper duplex mode</span>
00346 <span class="comment">        temp = enc28j60PhyRead(PHCON1);</span>
00347 <span class="comment">        temp &amp;= ~PHCON1_PDPXMD;</span>
00348 <span class="comment">        enc28j60PhyWrite(PHCON1, temp);</span>
00349 <span class="comment">        // Set the MAC to the proper duplex mode</span>
00350 <span class="comment">        temp = enc28j60Read(MACON3);</span>
00351 <span class="comment">        temp &amp;= ~MACON3_FULDPX;</span>
00352 <span class="comment">        enc28j60Write(MACON3, temp);</span>
00353 <span class="comment">    }</span>