smdk2510.c

VxWorks BSP for S3C2510A

		DBG("\n[1]Memory Space,	");
	if(sPCIHCMD.BME)
		DBG("\n[2]Bus Master	");
	if(sPCIHCMD.SCE)
		DBG("\n[3]Special Cycle ,	");
	if(sPCIHCMD.MWI)
		DBG("\n[4]Memory Write and Invalidate,	");
	if(sPCIHCMD.VGA)
		DBG("\n[5]VGA palette Snoop	");
	if(sPCIHCMD.PEE)
		DBG("\n[6]Parity Error Response,	");
	if(sPCIHCMD.STC)
		DBG("\n[7]Stepping Control ,	");
	if(sPCIHCMD.SER)
		DBG("\n[8]SERR# Enable ,	");
	if(sPCIHCMD.FBE)
		DBG("\n[9]Fast Back to Back Enable  ,	");
	if(sPCIHCMD.CAP)
		DBG("\n[4] Capabilities List	");
	if(sPCIHCMD.M66)
		DBG("\n[5]66MHz Capable ,	");
	if(sPCIHCMD.FBC)
		DBG("\n[7]Fast Back to Back Capable  ,	");
	if(sPCIHCMD.MPE)
		DBG("\n[8]Master Data Parity Error  ,	");
	if(sPCIHCMD.DST==0)
		DBG("\n[9] DEVSEL = Fast,	");
	else if(sPCIHCMD.DST==1)
		DBG("\n[9] DEVSEL = Medium,	");
	else 	if(sPCIHCMD.DST==2)
		DBG("\n[9] DEVSEL = Slow,	");
	if(sPCIHCMD.STA)
		DBG("\n[11]Signaled Target Abort  ,	");
	if(sPCIHCMD.RTA)
		DBG("\n[12]Received Target Abort ,	");
	if(sPCIHCMD.RMA)
		DBG("\n[13]Received Master Abort ,	");
	if(sPCIHCMD.SSE)
		DBG("\n[14]Signaled System Error ,	");
	if(sPCIHCMD.DPE)
		DBG("\n[15]Detected Parity Error ,	");
 	DBG("\n------------------------------------------------------	");
}

void ISR_Timer_NormalOn(void)
{
	static unsigned long timer_count = 0x0;

	if(timer_count >= 0x8) timer_count = 0x0;
	if(timer_count == 0x0) IIOPDATA1 = 0x7e;
	else if(timer_count == 0x1) IIOPDATA1 = 0xbd;
	else if(timer_count == 0x2)	IIOPDATA1 = 0xdb;
	else if(timer_count == 0x3) IIOPDATA1 = 0xe7;
	else if(timer_count == 0x4) IIOPDATA1 = 0xe7;
	else if(timer_count == 0x5) IIOPDATA1 = 0xdb;
	else if(timer_count == 0x6) IIOPDATA1 = 0xbd;
	else IIOPDATA1 = 0x7e;
	timer_count++;
}
/*
static void ISR_PCI_Timer5_NormalOn(int irq, void *dev_id, struct pt_regs *regs) 
{TimerInterruptClear(TIMER5);   ISR_PCI_Timer_NormalOn(); }
*/

static void	ISR_PCI(int irq, void *dev_id, struct pt_regs *regs)
{
 	PCI_PCISCR_View(); 
	PCI_PCIINTST_View();
	rPCIHSC |=  0xffff0000;
 
	//PCI_PCIINTEN_View();
}
static void ISR_Timer0_NormalOn(int irq, void *dev_id, struct pt_regs *regs) 
{ TimerInterruptClear(TIMER0); ISR_Timer_NormalOn();}
static void ISR_Timer1_NormalOn(int irq, void *dev_id, struct pt_regs *regs) 
{ TimerInterruptClear(TIMER1); ISR_Timer_NormalOn();}
static void ISR_Timer2_NormalOn(int irq, void *dev_id, struct pt_regs *regs) 
{ TimerInterruptClear(TIMER2); ISR_Timer_NormalOn();}
static void ISR_Timer3_NormalOn(int irq, void *dev_id, struct pt_regs *regs) 
{ TimerInterruptClear(TIMER3); ISR_Timer_NormalOn();}
static void ISR_Timer4_NormalOn(int irq, void *dev_id, struct pt_regs *regs) 
{ TimerInterruptClear(TIMER4); ISR_Timer_NormalOn();}
static void ISR_Timer5_NormalOn(int irq, void *dev_id, struct pt_regs *regs) 
{ TimerInterruptClear(TIMER5); ISR_Timer_NormalOn();}


void TimerData(unsigned long device, unsigned long msec)
{
    TTDATA(device) = gBUSCLK/1000*msec;
}

void TimerNormalOn(unsigned long device, unsigned long msec)
{
    switch(device)
    {
        case 0: request_irq(nTIMER0, &ISR_Timer0_NormalOn,(u32)NULL,"ISR_TIMER0",NULL);  break;
        case 1: request_irq(nTIMER1, &ISR_Timer1_NormalOn,(u32)NULL,"ISR_TIMER1",NULL);  break;
        case 2: request_irq(nTIMER2, &ISR_Timer2_NormalOn,(u32)NULL,"ISR_TIMER2",NULL);  break;
        case 3: request_irq(nTIMER3, &ISR_Timer3_NormalOn,(u32)NULL,"ISR_TIMER3",NULL);  break;
        case 4: request_irq(nTIMER4, &ISR_Timer4_NormalOn,(u32)NULL,"ISR_TIMER4",NULL);  break;
        case 5: request_irq(nTIMER5, &ISR_Timer5_NormalOn,(u32)NULL,"ISR_TIMER5",NULL);  break;
        default: request_irq(nTIMER5, &ISR_Timer5_NormalOn,(u32)NULL,"ISR_TIMER5",NULL);  break;
    }

    TimerInterval(device);
    TimerData(device, msec);
    TimerStart(device);

    switch(device)
    {
        case 0: Enable_Int(INT_IRQ_TIMER0);     break;
        case 1: Enable_Int(INT_IRQ_TIMER1);     break;
        case 2: Enable_Int(INT_IRQ_TIMER2);     break;
        case 3: Enable_Int(INT_IRQ_TIMER3);     break;
        case 4: Enable_Int(INT_IRQ_TIMER4);     break;
        case 5: Enable_Int(INT_IRQ_TIMER5);     break;
        default:    Enable_Int(INT_IRQ_TIMER5);     break;
    }

    GlobalEn_Int();
}

//ryc----------------------------------
void	ISR_Gdma0ForPCItest(int irq, void *dev_id, struct pt_regs *regs)
{
	DBG("\n** ISR_Gdma0 performed.") ;
	DIPR(0)=GDMAPENDING_CLR;
	DBG("\nDSAR0[0x%x], DDAR0[0x%x], DTCR0[0x%x]", DSAR(0), DDAR(0), DTCR(0));
}
void	ISR_Gdma1ForPCItest(int irq, void *dev_id, struct pt_regs *regs)
{

	DBG("\n** ISR_Gdma1 performed.") ;
	DIPR(1)=GDMAPENDING_CLR;
	DBG("\nDSAR1[0x%x], DDAR1[0x%x], DTCR1[0x%x]", DSAR(1), DDAR(1), DTCR(1));

 }
void	ISR_Gdma2ForPCItest(int irq, void *dev_id, struct pt_regs *regs)
{
	DBG("\n** ISR_Gdma2 performed.") ;
	DIPR(2)=GDMAPENDING_CLR;
	DBG("\nDSAR2[0x%x], DDAR2[0x%x], DTCR2[0x%x]", DSAR(2), DDAR(2), DTCR(2));
}
void	ISR_Gdma3ForPCItest(int irq, void *dev_id, struct pt_regs *regs)
{
	DBG("\n** ISR_Gdma3 performed.") ;
	DIPR(3)=GDMAPENDING_CLR;
	DBG("\nDSAR3[0x%x], DDAR3[0x%x], DTCR3[0x%x]", DSAR(3), DDAR(3), DTCR(3));
}
void	ISR_Gdma4ForPCItest(int irq, void *dev_id, struct pt_regs *regs)
{
	DBG("\n** ISR_Gdma4 performed.") ;
	DIPR(4) = GDMAPENDING_CLR;
	DBG("\nDSAR4[0x%x], DDAR4[0x%x], DTCR4[0x%x]", DSAR(4), DDAR(4), DTCR(4));
}
void	ISR_Gdma5ForPCItest(int irq, void *dev_id, struct pt_regs *regs)
{
	DBG("\n** ISR_Gdma5 performed.") ;
	DIPR(5) = GDMAPENDING_CLR;
	DBG("\nDSAR5[0x%x], DDAR5[0x%x], DTCR5[0x%x]", DSAR(5), DDAR(5), DTCR(5));
}

void PCI_SFR_Register_Display(void)
{
	u32 offset,i;

	printk("PCI_SFR_Register_Display\n");
	printk("-----------------------------\n");
	for(offset =0,i=0 ; offset < 0xe4 ; offset+=4,i++){
		if(!(i%4)) printk("\n");
		printk("[0x%2.2ux] = %8.2lux", offset,r32(PCIHID + offset));
	}
	printk("\n-----------------------------\n");
}
void PCI_BIF_Register_Display(void)
{
	u32 offset,i;

	printk("\nPCI_BIF_Register_Display\n");
	printk("\n-----------------------------\n");
	for(offset =0,i=0 ; offset < 0xb4 ; offset+=4,i++){
		if(!(i%4)) printk("\n");
		printk("[0x%2.2lx] = %8.2lx", offset,r32(PCICON + offset));
	}
	printk("\n-----------------------------\n");
}
/* ryc++ for using external clock */
//#define __PCI_EXT_CLK 1
void __init SMDK2510_PCI_Setup(void)
{

		/* Disable PCI interrupt enable registers */
		rPCIINTEN = 0x0; 

		/* we don't user External Arbitor,External clock,Externel PCI reset */	
#ifndef __PCI_EXT_ARB
		rPCICON |= PCIARBITOR_INT;
#else
		DBG("External Arbitor set\n");
#endif

#ifdef __PCI_EXT_CLK
		rPCIDIAG0 |= PCICLK_EXT;
		printk("External Clock is used !!!\n");
#else
		rPCIRCC |= PCICLK_33M;
		DBG("\nInternal Clock. PCIRCC.M33[%x], SYSCFG[%x], SPLL[%x],UPLL[%x]",sPCIRCC.M33, SYSCFG,SPLL,UPLL);
#endif

#ifdef __PCI_EXT_RST
		rPCIDIAG0 |= PCIRESET_EXT;
		DBG("   External PCI Reset\n");
#endif


#ifdef __PCI_EXT_PULLUP
		rPCIDIAG0 |= PCIPULLUP_EXT;
		DBG("   External PCI Pull-up\n");
#endif

		rPCIRCC &= ~PCIRESETCLK_MASK;

		rPCIRCC |= PCILOG_RESET;
		rPCIRCC |= PCIBUS_RESET;

	PCI_Delay(13300000);    // to wait for target to ready	

	/* default value(0x0d8000) was for wireless controller, so ryc changed 
	 * the class code field to set Host bridge(0x060000).
	 */
	rPCIHCODE = 0x06000001; // set Host bridge
	// Initialize PCI Configuration space registers
	rPCIHCMD |= PCIBUSMASTER_ENABLE + PCIMWI_ENABLE + PCIPERR_RESPONSE_ENABLE 
				+ (AgentMode()? PCISERR_ENABLE:0);


	rPCIBAM0 = 0xfe000000;
	rPCIINTEN = 0xffffffff; //all enable for viewing status.
	rPCICON |= PCICONFIG_DONE + PCISYSTEMREAD_READY;

	/* Memory Burst Read enable(Burst Read decrease its performance).*/
	sPCICON.MMP = 1;

	rPCIHSTS |= PCISTATUS_ALL; // rPCISCR All status clear

	// rPCIINTST All status clear
	rPCIINTST = ALL_WRITE1CLR;
	sPCIBELPA.BEL = WRITE0CLR;

	Enable_Int(INT_IRQ_PCI_PCCARD);
}

/* Initialization routine for S3C2510 chipset */
void __init pci_host_controller_init(void)
{
	printk("S3C2510 PCI Host Controller Initializing...\n");

	/* check mode */
	if(PCIMode()) /* Check if PCI host mode or not */
		SMDK2510_PCI_Setup();


}

void __init PCI_SfrDisplay(void)
{
	u32 i,pciData;

	DBG("SFR addr(Name)  Current_Value\n");
	for(i=0;i<NUM_OF_PCISFR;i++)
	{
		pciData = *(u32*)(pci_sfr[i].addr);
		DBG("%10x(%10s)    %10x\n",pci_sfr[i].addr,pci_sfr[i].name
				,pci_sfr[i].ResetValue);
	}
}
 /*
  *  pci host initialize & scan bus routine. 
  */ 
void __init smdk2510_pci_init(void *sysdata)
{
	u32 dummy;

	dummy = 0xa510;
	/* Initialize S3C2510 chipset for PCI host operation */
	pci_host_controller_init();

	/* kernel scan bus for detecting devices */
	pci_scan_bus(0,&smdk2510_pci_ops,sysdata);

	if(request_irq(SRC_IRQ_PCI_PCCARD,&ISR_PCI, SA_SHIRQ,"ISR_PCI", &dummy)) {
		printk("Unable to get irq(%d)\n",SRC_IRQ_PCI_PCCARD);
	}
}

/*
 *  smdk2510_pci_setup_resources
 *  @*resource : resource structure point for mapping to root->resource
 */
void __init smdk2510_pci_setup_resources(struct resource **resource)
{
	
	struct resource *mem_mem;

	mem_mem = kmalloc(sizeof(*mem_mem), GFP_KERNEL);
	memset(mem_mem, 0, sizeof(*mem_mem));


	mem_mem->flags = IORESOURCE_MEM;
	mem_mem->name  = "SMDk2510 PCI MEM Region";

	allocate_resource(&iomem_pci_resource, mem_mem, 0x20000000,
			  0x00000000, 0xfffffffe, 0x20000000, NULL, NULL);
	resource[0] = &ioport_resource;
	resource[1] = mem_mem;
	resource[2] = NULL;
	
}

/* 
 * CardBus related functions. 
 */

#define DEASSERT_LOGIC_RESET    (sPCIRCC.RSL=1)
#define DEASSERT_RESET  (sPCIRCC.RSB=1)

#define CHECK_CCD   ((sPCCARDPRS.CD1 && sPCCARDPRS.CD2)? 0:1) 
#define     TYPE_CARDBUS    0x1

#define     THREE_VOLTAGE   0x33
#define     FIVE_VOLTAGE    0x50

#define PROVIDE_VCC(n) { sPCCARDCON.VCC=0; if(n==THREE_VOLTAGE) sPCCARDCON.VCC=3; else if (n==FIVE_VOLTAGE) sPCCARDCON.VCC=2;}

int SMDK2510_CardBus_Setup(void)
{
    unsigned int flags;

    save_flags(flags);
    cli();

    /* STEP 1. internal arbiter ON, auto-adress translation ON */
    sPCICON.ARB=1;
    sPCICON.ATS=1;
    sPCICON.RDY =1;

    /* STEP 2. clock UN-mask, auto-clkrun signal */
    //sPCIDIAG0.EXC=1;    /* use external clock */
    sPCIDIAG0.EXC=0;    /* use internal clock */
    sPCIDIAG0.NPU=1;

    sPCIRCC.MSK=0;
    sPCIRCC.M33=0;
    sPCIRCC.ACC=1;

    /* STEP 3 assert pci logic reset */
    sPCIRCC.RSL=1;

    /*
     * STEP 4 setting interrupt-related registers 
     * event mask (0->mask, 1->Unmask)
     * all is unmasked
     * and then pc-card event interrupt enable, all pci interrupt enable also.
     */
    sPCCARDEVM.STC=1;
    sPCCARDEVM.CD1=1;
    sPCCARDEVM.CD2=1;
    sPCCARDEVM.PWC=1;

    sPCIINTEN.PME=1;

	/* mask value to cover SDRAM size (32M == 0x2000000) */
    rPCIBAM0 = 0xfe000000;

    /*
     * 1. test whether cards are already present or not
     * 2. apply Vcc
     * 3. release bus & logic reset
     * 4. enable pc-card interrupts
     * 5. set configuration done
     */


    if(!CHECK_CCD || !sPCCARDPRS.C32) {
        printk( "No card, or not CardBus card.\n");
        return -1;
    }

    printk("CardBus Card is detected: ");

    /* apply appropriate Vcc for card */
    if(sPCCARDPRS.C3V)
    {
        PROVIDE_VCC(THREE_VOLTAGE);
        printk("3 Voltage Card\n");
    }
    else if(sPCCARDPRS.C5V)
    {
        PROVIDE_VCC(FIVE_VOLTAGE);
        printk("5 Voltage Card\n");
    }


    /* wait for card active state */
    while(!sPCCARDCON.ACT)
        ;

    /* deassert logic & bus reset */
    DEASSERT_LOGIC_RESET;
    DEASSERT_RESET;

	PCI_Delay(13300000);    // to wait for target to ready  

    /* all pc-card interrupts enable */
    rPCIINTST = 0xffffffff;
    rPCIINTEN = 0xffffffff;

    /* configuration done */
    sPCICON.CFD=1;

    /* initialize BARs */
    sPCIHSC.CMD=0x7;

    restore_flags(flags);
	return 0;
}


int __init cardbus_controller_init(void)
{
	int ret = -1;
    printk("CardBus Host Controller Initializing...\n");

    /* First, it is checked whether the mode is CardBus or not. */
    if(!PCIMode())
        ret = SMDK2510_CardBus_Setup();
	return ret;
}

void __init smdk2510_cardbus_init(void *sysdata)
{
    if (!cardbus_controller_init())		/* check whether there is a card or not. */
		pci_scan_bus(0,&smdk2510_pci_ops,sysdata);
}