smdk2510.c

VxWorks BSP for S3C2510A

/*
 *  edited by Roh you-chang
 *  
 *  Copyright (C) 2002-2004 SAMSUNG ELECTRONIS
 *
 *  CardBus functions are added.  WG.Kim 2002, 10
 *       
 */
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/ptrace.h>
#include <linux/interrupt.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/ioport.h>

#include <asm/arch/hardware.h>

#define GDMAPENDING_CLR 0x1 
#define gBUSCLK 0
#define BEL_MESSAGE 0x7fffffff
#define PDMA_CH0 0x0
#define PDMA_CH1 0x1

//#define MAX_SLOTS	21 //ryc-- 
//#define DEBUG  //ryc--

#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif
#define NUM_OF_PCISFR 46

static s_SFR pci_sfr[NUM_OF_PCISFR] = {
	{ (void *)0xf0110000,(char*)"PCIHID" , (u32)0xa510144d, (u32)0 },
	{ (void *)0xf0110004, (char*)"PCIHSC"  ,   (u32)0x02b00000, (u32)0 },
	{ (void *)0xf0110008, (char*)"PCIHCODE",   (u32)0x0d800001, (u32)0 },
	{ (void *)0xf011000c, (char*)"PCIHLINE",  (u32)0x00000000, (u32)0 },
	{ (void *)0xf0110010, (char*)"PCIHBAR0" ,   (u32)0x00000008, (u32)0 },
	{ (void *)0xf0110014, (char*)"PCIHBAR1" ,   (u32)0x00000008, (u32)0 },
	{ (void *)0xf0110018, (char*)"PCIHBAR2",    (u32)0x00000001, (u32)0 },
	{ (void *)0xf011002c, (char*)"PCIHSSID", (u32)0xa510144d, (u32)0 },
	{ (void *)0xf0110034, (char*)"PCIHCAP"  ,  (u32)0x000000dc, (u32)0 },
	{ (void *)0xf011003c, (char*)"rPCIHLTIT",  (u32)0x00000000, (u32)0 },
	{ (void *)0xf0110040, (char*)"rPCIHTIMER"  ,  (u32)0x00008080, (u32)0 },
	{ (void *)0xf01100dc, (char*)"rPCIHPMR0"  ,  (u32)0x7e020001, (u32)0 },
	{ (void *)0xf01100e0, (char*)"rPCIHPMR1"  ,  (u32)0x7e020001, (u32)0 },
	{ (void *)0xf0110100, (char*)"PCICON"   , (u32)0x000000b1, (u32)0 },
	{ (void *)0xf0110104, (char*)"PCISET"  , (u32)0x00000400, (u32)0 },
	{ (void *)0xf0110108, (char*)"PCIINTEN",  (u32)0x0, (u32)0 },
	{ (void *)0xf011010c, (char*)"PCIINTST",  (u32)0x0, (u32)0 },
	{ (void *)0xf0110110, (char*)"PCIINTAD",  (u32)0x0, (u32)0 },
	{ (void *)0xf0110114, (char*)"PCIBATAPM", (u32)0x0, (u32)0 },
	{ (void *)0xf0110118, (char*)"PCIBATAPI", (u32)0x0, (u32)0 },
	{ (void *)0xf011011C, (char*)"PCIRCC"  , (u32)0x4000000c, (u32)0 },
	{ (void *)0xf0110120, (char*)"PCIDIAG0"  , (u32)0x00000000, (u32)0 },
	{ (void *)0xf0110124, (char*)"PCIDIAG1"  , (u32)0x00000000, (u32)0 },
	{ (void *)0xf0110128, (char*)"PCIBELAP"  , (u32)0x00000000, (u32)0 },
	{ (void *)0xf011012c, (char*)"PCIBELPA"  , (u32)0x00000000, (u32)0 },
	{ (void *)0xf0110130, (char*)"PCIMAIL0"  , (u32)0x00000000, (u32)0 },
	{ (void *)0xf0110134, (char*)"PCIMAIL1"  , (u32)0x00000000, (u32)0 },
	{ (void *)0xf0110138, (char*)"PCIMAIL2"  , (u32)0x00000000, (u32)0 },
	{ (void *)0xf011013c, (char*)"PCIMAIL3"  , (u32)0x00000000, (u32)0 },
	{ (void *)0xf0110140, (char*)"PCIBATPA0", (u32)0x0, (u32)0 },
	{ (void *)0xf0110144, (char*)"PCIBAM0" ,  (u32)0xffff0000, (u32)0 },
	{ (void *)0xf0110148, (char*)"PCIBATPA1", (u32)0xf0110000, (u32)0 },
	{ (void *)0xf011014c, (char*)"PCIBAM1",   (u32)0xfffffe00, (u32)0 },
	{ (void *)0xf0110150, (char*)"PCIBATPA2", (u32)0xf0110100, (u32)0 },
	{ (void *)0xf0110154, (char*)"PCIBAM2",	(u32)0xffffff00, (u32)0 },
	{ (void *)0xf0110158, (char*)"PCISWAP",	(u32)0x00000000, (u32)0 },
	{ (void *)0xf0110180, (char*)"PDMACON0",	(u32)0x00001000, (u32)0 },
	{ (void *)0xf0110184, (char*)"PDMASRC0",	(u32)0x00000000, (u32)0 },
	{ (void *)0xf0110188, (char*)"PDMADST0",	(u32)0x00000000, (u32)0 },
	{ (void *)0xf011018c, (char*)"PDMACNT0",	(u32)0x00000000, (u32)0 },
	{ (void *)0xf0110190, (char*)"PDMARUN0",	(u32)0x00000000, (u32)0 },
	{ (void *)0xf01101a0, (char*)"PDMACON1",	(u32)0x00001000, (u32)0 },
	{ (void *)0xf01101a4, (char*)"PDMASRC1",	(u32)0x00000000, (u32)0 },
	{ (void *)0xf01101a8, (char*)"PDMADST1",	(u32)0x00000000, (u32)0 },
	{ (void *)0xf01101ac, (char*)"PDMACNT1",	(u32)0x00000000, (u32)0 },
	{ (void *)0xf01101b0, (char*)"PDMARUN1",	(u32)0x00000000, (u32)0 }
};

unsigned long
PCIMakeConfigAddress(u32 bus, u32 device, u32 function, u32 offset)
{
	u32 address=0;

	if(bus == 0)
	{
		if(device != 0)
		{
			address = AHB_ADDR_PCI_CFG0(device, function, offset);
		}else{
			address = 0xf0110000;
			address |= offset & 0xff;
		}
	}else{
			address = AHB_ADDR_PCI_CFG1(bus, device, function, offset);
	}
	return address;
}

int
smdk2510_pci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
{
	unsigned int devfn = dev->devfn;
	u32 slot,func;
	u8* v;
	
	slot = PCI_SLOT(devfn);
	func = PCI_FUNC(devfn);

	v = (u8*)PCIMakeConfigAddress(dev->bus->number, slot, func, where);
	*value = *v;

	return PCIBIOS_SUCCESSFUL;
}

int
smdk2510_pci_read_config_word(struct pci_dev *dev, int where, u16 *value)
{
	unsigned int devfn = dev->devfn;
	u32 slot,func;
	u16* v;

	slot = PCI_SLOT(devfn);
	func = PCI_FUNC(devfn);
	
	v = (u16*)PCIMakeConfigAddress(dev->bus->number, slot, func, where);	
	*value = *v;

	return PCIBIOS_SUCCESSFUL;
}

int
smdk2510_pci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
{
	unsigned int devfn = dev->devfn;
	u32 slot,func;
	u32* v;

	slot = PCI_SLOT(devfn);
	func = PCI_FUNC(devfn);

	v = (u32*)PCIMakeConfigAddress(dev->bus->number, slot, func, where);	
	*value = *v;

	return PCIBIOS_SUCCESSFUL;
}

int
smdk2510_pci_write_config_byte(struct pci_dev *dev, int where, u8 value)
{
	
	unsigned int devfn = dev->devfn;
	u32 slot,func;
	u8* v;

	slot = PCI_SLOT(devfn);
	func = PCI_FUNC(devfn);

	v = (u8*)PCIMakeConfigAddress(dev->bus->number, slot, func, where);	
	*v = value;

	return PCIBIOS_SUCCESSFUL;
}

int
smdk2510_pci_write_config_word(struct pci_dev *dev, int where, u16 value)
{
	unsigned int devfn = dev->devfn;
	u32 slot,func;
	u16* v;

	slot = PCI_SLOT(devfn);
	func = PCI_FUNC(devfn);

	v = (u16*)PCIMakeConfigAddress(dev->bus->number, slot, func, where);	
	*v = value;

	return PCIBIOS_SUCCESSFUL;
}

int
smdk2510_pci_write_config_dword(struct pci_dev *dev, int where, u32 value)
{
	unsigned int devfn = dev->devfn;
	u32 slot,func;
	u32* v;

	slot = PCI_SLOT(devfn);
	func = PCI_FUNC(devfn);

	v = (u32*)PCIMakeConfigAddress(dev->bus->number, slot, func, where);	
	*v = value;

	return PCIBIOS_SUCCESSFUL;
}
static struct pci_ops smdk2510_pci_ops = {
	smdk2510_pci_read_config_byte,
	smdk2510_pci_read_config_word,
	smdk2510_pci_read_config_dword,
	smdk2510_pci_write_config_byte,
	smdk2510_pci_write_config_word,
	smdk2510_pci_write_config_dword,
};

void __init PCI_SfrStore(void)
{
	int i;
				  
	   	for(i=0;i<NUM_OF_PCISFR;i++) 
		{ 
			pci_sfr[i].InitializedValue = *(u32 *)(pci_sfr[i].addr);
			//DBG(" %10x(%10s)  %10x\n",pci_sfr[i].addr,pci_sfr[i].name,pci_sfr[i].InitializedValue);
		}
	
}

void __init PCI_Delay(unsigned long x)
{
	while(--x);
}

void ISR_PCI_Timer_NormalOn(void)
{
	static unsigned long timer_count = 0x0;
	unsigned long pciIopData = 0xfe;

	if(timer_count >= 0x8)
	{
		timer_count = 0x0;
		pciIopData = (pciIopData<<1);
	}
	else
		pciIopData = (pciIopData<<1)+1;

	IIOPDATA1 = pciIopData;
	timer_count++;
#ifdef __PCI_WATCHDOG_RESET	 // currently disabled
	if(pciIsPciSetup)	WATCHDOG=0xe0004000;
#endif // __PCI_WATCHDOG_RESET	
}

void PCI_PDMA_View(u8 ch)
{
 	DBG("\n---PCI_PDMA[%d]_View-------------------------------------   ",ch);

	if(sPDMACON(ch).RE)
	 	DBG("\n[0]PDMA Running... 	");

	if(sPDMACON(ch).IRP)
		DBG("\n[1]Route INT to INTA# 	");
	if(sPDMACON(ch).BSE)
	 	DBG("\n[2]Byte Swap (PCI to PCI, word boudary)	");
	if(sPDMACON(ch).S)
	{
		DBG("\n[4]Source Direction : PCI	");
	 	DBG("\n[11:8]Src Commnad : %s",((sPDMACON(ch).SCM>>1)==0x3) ? "Mem" : "I/O" );
	}
	else 	
	 	DBG("\n[4]Source Direction : AHB 	");

	if(sPDMACON(ch).D)
	{
		DBG("\n[5]Dst Direction : PCI	");
	 	DBG("\n[11:8]Dst Commnad : %s",((sPDMACON(ch).DCM>>1)==0x3) ? "Mem" : "I/O" );
	}
	else 	
	 	DBG("\n[5]Dst Direction : AHB 	");

	if(sPDMACON(ch).SAF)
	 	DBG("\n[6]Src Addr Fixed 	");

	if(sPDMACON(ch).DAF)
	 	DBG("\n[7]Dst Addr Fixed 	");


	if(sPDMACON(ch).ERR)
		{
	 	DBG("\n[0]Done w/ Error 	");
#ifdef __PCI_STOP_AT_ERROR
		GlobalDis_Int(); GlobalEn_Int();
#endif //__PCI_STOP_AT_ERROR
		}
	if(sPDMACON(ch).PRG)
	 	DBG("\n[0]PDMA Programmed by PCI	");
	if(sPDMACON(ch).BSY)
	 	DBG("\n[0]PDMA[%x] Running... 	",ch);

	 	DBG("\nPDMA Src[%x] Addr 		: %8x", ch, rPDMASRC(ch));
	 	DBG("\nPDMA Dst[%x] Addr 		: %8x", ch, rPDMADST(ch));
	 	DBG("\nPDMA Transfer Byte Count[%x] : %8x", ch, rPDMACNT(ch));

 	DBG("\n");
 	
}
void PCI_PCIINTST_View(void)
{
    union { u32 pci_32;  s_PCIINTST s; } uPciIntSt;
	unsigned long pciBellMessage;
	u32 pciExerAddr,pciExerCmd,pciExerIntAddr,pciExerNod; //ryc++
	u32 pciPdma0Available=1;

	uPciIntSt.pci_32 = rPCIINTST;
	rPCIINTST = uPciIntSt.pci_32;

 	DBG("\n---PCI_PCIINTST_View-------------------------------------	");
 
	if(uPciIntSt.s.PRD)
		{
	 	DBG("\n[0]PCI Reset DeAsseerted	");
		}	 	
	if(uPciIntSt.s.PRA)
		{	
		DBG("\n[1]PCI Reset Asserted ,	");
		}
	if(uPciIntSt.s.MFE)
		{
		DBG("\n[2]Master Fatal Error , PCIINTAD[0x%lx]",rPCIINTAD);
#ifdef __PCI_STOP_AT_ERROR
		//GlobalDis_Int(); GlobalEn_Int();
#endif //__PCI_STOP_AT_ERROR 
		}
	if(uPciIntSt.s.MPE)
	{
		printk("\n[3]Master Parity Error , PCIINTAD[0x%lx]",rPCIINTAD);
#ifdef __PCI_STOP_AT_ERROR
		GlobalDis_Int(); GlobalEn_Int();
#endif //__PCI_STOP_AT_ERROR
	}		
	if(uPciIntSt.s.TPE)
	{
		printk("\n[4]Target Parity Error ,	");
#ifdef __PCI_STOP_AT_ERROR
		GlobalDis_Int(); GlobalEn_Int();
#endif //__PCI_STOP_AT_ERROR
	}

	if(uPciIntSt.s.PME && HostMode())
	{
		DBG("\n[5]PME# Asserted  ,	");
#ifdef __PCI_STOP_AT_ERROR
		GlobalDis_Int(); GlobalEn_Int();
#endif //__PCI_STOP_AT_ERROR 
	}
	if(uPciIntSt.s.PME && AgentMode())
		DBG("\n[5]Change of PME_enbale bit 0 to 1 in the PMCSR ,	");
		
	if(uPciIntSt.s.PMC && AgentMode())
		DBG("\n[6]PME_Status bit is cleard ,	");
	if(uPciIntSt.s.PSC && AgentMode())
		DBG("\n[7]Power Status Changed ,	");
	if(uPciIntSt.s.BPA && sPCIINTEN.BPA)
	{
		DBG("\n[8]Door Bell to AHB ,	");
		pciBellMessage = rPCIBELPA & BEL_MESSAGE;
		switch(pciBellMessage)
		{
			case 1: //EXERCISER_START:
					pciExerAddr = rPCIMAIL0;
					pciExerCmd = rPCIMAIL1;
					pciExerIntAddr = rPCIMAIL2;
					pciExerNod = rPCIMAIL3;
					DBG("\n PCI Bell Message [EXERCISER_START]\n pciExerAddr[0x%x]\n pciExerCmd[0x%x]\n pciExerIntAddr[0x%x]\n pciExerNod[0x%x]", pciExerAddr, pciExerCmd, pciExerIntAddr, pciExerNod);
					
					break;
					
			case 2: //EXERCISER_STOP:
					DBG("\n Bell Message [EXERCISER_STOP]");
					break;
					
			default : DBG("\nUnknown Door Bell Message[%x]",pciBellMessage);
#ifdef __PCI_STOP_AT_ERROR
		GlobalDis_Int(); GlobalEn_Int();
#endif //__PCI_STOP_AT_ERROR
		}
		rPCIBELPA = rPCIMAIL0 = rPCIMAIL1 = rPCIMAIL2 = rPCIMAIL3 =0;
	}
	if(uPciIntSt.s.SER)
	{
			DBG("\n[9]SERR# Asserted  ,	");
	}
	if(uPciIntSt.s.INA)
	{
		DBG("\n[10]INTA# Asserted  ,	");
#ifdef __PCI_STOP_AT_ERROR
		GlobalDis_Int(); GlobalEn_Int();
#endif //__PCI_STOP_AT_ERROR 
	}
	if(uPciIntSt.s.DM0)
	{
		DBG("\n[12]PDMA0 Done ,	");
		pciPdma0Available = 1;

		PCI_PDMA_View(PDMA_CH0);
	}
	
	if(uPciIntSt.s.DE0)
	{
		printk("\n[13]PDMA0 Error  ,	");
		PCI_PDMA_View(PDMA_CH0);
#ifdef __PCI_STOP_AT_ERROR
		GlobalDis_Int(); GlobalEn_Int();
#endif //__PCI_STOP_AT_ERROR

	}
	
	if(uPciIntSt.s.DM1)
	{
		DBG("\n[14]PDMA1 Done ,	");

		PCI_PDMA_View(PDMA_CH1);
	}
	
	if(uPciIntSt.s.DE1)
	{
		printk("\n[15]PDMA1 Error ,	");
		PCI_PDMA_View(PDMA_CH1);
#ifdef __PCI_STOP_AT_ERROR
		GlobalDis_Int(); GlobalEn_Int();
#endif //__PCI_STOP_AT_ERROR
	}

	if(uPciIntSt.s.AER)
		printk("\n[16]AHB Error Response  ,	");
	if(uPciIntSt.s.RDE)
		//printk("\n[30]Read Error ,	");
	if(uPciIntSt.s.WRE)
		printk("\n[31]Write Error ,	");
 	DBG("\n------------------------------------------------------	");

}
void PCI_PCISCR_View(void)
{
   union { u32 pci_32;  s_PCIINTST s; } uPciScrSt;

	uPciScrSt.pci_32 = rPCIHSC;

 	DBG("\n---PCI_PCISCR_View------------------------------------	");
	if(sPCIHCMD.IOE)
	 	DBG("\n[0]I/O Space 	");
	if(sPCIHCMD.MME)