📄 s3c2510pci_def.h
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unsigned int PSC:1; /* Bit 7 (PSC) : Power State Changed*/ unsigned int BPA:1; /* Bit 8 (BPA) : PCI Doorbell Register to AHB*/ unsigned int SER:1; /* Bit 9 (SER) : PCI bus SERR# if PCICON[HST]=1*/ unsigned int INA:1; /* Bit 10 (INA) : PCI bus INTA# if PCICON[HST]=1*/ unsigned int rs0:1; /* Bit 11 (rs0)*/ unsigned int DM0:1; /* Bit 12 (DM0) : PDMA Channel 0 Done*/ unsigned int DE0:1; /* Bit 13 (DE0) : PDMA Channel 0 Error*/ unsigned int DM1:1; /* Bit 14 (DM1) : PDMA Channel 1 Done*/ unsigned int DE1:1; /* Bit 15 (DE1) : PDMA Channel 1 Error*/ unsigned int AER:1; /* Bit 16 (AER) : AHB ERROR response*/ unsigned int rs1:12; /* 28- 17 (rs1)*/ unsigned int DME:1; /* Bit 29 (DME) : DMA Err of PCIINTST[MFE,MPE]*/ unsigned int RDE:1; /* Bit 30 (RDE) : Write Err of PCIINTST[MFE,MPE]*/ unsigned int WRE:1; /* Bit 31 (WRE) : Read Err of PCIINTST[MFE,MPE]*/}s_PCIINTST;typedef union { s_PCIINTST sfr; unsigned int u32;} u_PCIINTST;/* PCIBATAPM (114h) PCI Base Address to PCI bus (Memory region) */typedef struct { unsigned int rs0:28; /* 27 - 0 (rs0)*/ unsigned int APM:4; /* 31 -28 (APM) : Base Address*/}s_PCIBATAPM;/* PCIBATAPI (118h) PCI Base Address to PCI bus (I/O region) */typedef struct { unsigned int rs0:26; /* 25 - 0 (rs0)*/ unsigned int API:6; /* 31 -26 (APM) : Base Address*/}s_PCIBATAPI;/* PCIRCC (11C) Host Mode Reset & Clock Control Register */typedef struct { unsigned int RSB:1; /* Bit 0 (RSB) : P&C Bus Reset (low active) */ unsigned int RSL:1; /* Bit 1 (RSL) : P&C Logic Reset (low active) */ unsigned int MSK:1; /* Bit 2 (MSK) : P&C Clock/Bus Reset Mask */ unsigned int M33:1; /* Bit 3 (33M) : PCI Clock 33MHz Mode*/ unsigned int SLW:1; /* Bit 4 (SLW) : Slow Clock Mode(if CLKRUN#=1) */ unsigned int rs0:3; /* 7 - 5 (rs0)*/ unsigned int KCK:1; /* Bit 8 (KCK) : Keep Clock Mode(no stop) */ unsigned int ACC:1; /* Bit 9 (ACC) : Automatic CLKRUN# Control */ unsigned int CKI:1; /* Bit 10 (CKI) : CLKRUN# Event by ARM intrpt*/ unsigned int CKR:1; /* Bit 11 (CKR) : CLKRUN# Run by Event [CKI] */ unsigned int CKA:1; /* Bit 12 (CKA) : CLKRUN# Assert (Run Clock) */ unsigned int CKD:1; /* Bit 13 (CKD) : CLKRUN# Deassert (Stop Clock) */ unsigned int rs1:14; /* 27- 14 (rs1)*/ unsigned int BRS:1; /* Bit 28 (BRS) : P&C Bus Reset Status */ unsigned int LRS:1; /* Bit 29 (LRS) : Internal Logic Reset Status*/ unsigned int CKS:1; /* Bit 30 (CKS) : P&C Clock Status */ unsigned int CKN:1; /* Bit 31 (CKN) : CLKRUN# Status of last clock */}s_PCIRCC;#define PCIBUS_RESET (1<<0)#define PCILOG_RESET (1<<1)#define PCIRESETCLK_MASK (1<<2)#define PCICLK_33M (1<<3)/* PCIDIAG0 (120h) PCI Diagnostic Register 0*/typedef struct { unsigned int CMR:1; /* Bit 0 (CMR) : Use Common P&C Reset */ unsigned int EXR:1; /* Bit 1 (EXR) : Use external P&C reset*/ unsigned int EXC:1; /* Bit 2 (EXC) : Use external P&C clock*/ unsigned int IGB:1; /* Bit 3 (IGB) : Ignore byte enable for burst*/ unsigned int WPR:1; /* Bit 4 (WPR) : Write data regardless of perr*/ unsigned int NPU:1; /* Bit 5 (NPU) : Disable Pull-Up resistors*/ unsigned int FAS:1; /* Bit 6 (FAS) : Enable Fast Decoder */ unsigned int SPC:1; /* Bit 7 (SPC) : Short Power-cycle mode */ unsigned int FTR:1; /* Bit 8 (FTR) : Force to flush the TRCV FIFO*/ unsigned int FTT:1; /* Bit 9 (FTT) : Force to flush the TXMT FIFO */ unsigned int FMR:1; /* Bit 10 (FMR) : Force to flush the MRCV FIFO */ unsigned int FMT:1; /* Bit 11 (FMT) : Force to flush the MXMT FIFO */ unsigned int DI4:1; /* Bit 12 (DI4) : Disable INCR4 on AHB master */ unsigned int DIR:1; /* Bit 13 (DIR) : Disable Internal Retry Mech*/ unsigned int OBE:1; /* Bit 14 (OBE) : Original PCI Read BE Output*/ unsigned int X15:1; /* Bit 15 (X15) : Extra Diagnostic Control */ unsigned int X16:1; /* Bit 16 (X16) : Extra Diagnostic Control */ unsigned int X17:1; /* Bit 17 (X17) : Extra Diagnostic Control */ unsigned int X18:1; /* Bit 18 (X18) : Extra Diagnostic Control */ unsigned int X19:1; /* Bit 19 (X19) : Extra Diagnostic Control */ unsigned int rs0:12; /* 31 -20 (rs0)*/}s_PCIDIAG0;#define PCIRESET_EXT (1<<1)#define PCICLK_EXT (1<<2)#define PCIPULLUP_EXT (1<<5)/* PCIDIAG1 (124h) PCI Diagnostic Register 1*/typedef struct { unsigned int rs0:15; /* 14 - 0 (rs0)*/ unsigned int RSL:1; /* Bit 15 (RSL) : PCIRCC[RSL] Value Reset*/ unsigned int BID:2; /* 17 -16 (BID) : Last Accessed BAR Number */ unsigned int REQ:1; /* Bit 18 (REQ) : PCI Master Request Remains */ unsigned int MAS:5; /* 23 -19 (MAS) : PCI Master State */ unsigned int TAR:4; /* 27 -24 (TAR) : PCI Target State */ unsigned int REV:4; /* 31 -28 (REV) : Revision No. */}s_PCIDIAG1;/* PCIBELAP (128h) PCI Doorbell Register to PCI bus*//* PCIBELPA (12Ch) PCI Doorbell Register to AHB bus*/typedef struct { unsigned int UIF:31; /* 30 - 0 (UIF) : User Information*/ unsigned int BEL:1; /* Bit 31 (BEL) : Force interrupt*/}s_PCIBEL;/* PCISWAP (158h) Byte Swap Register*/typedef struct { unsigned int TRB:2; /* 1 - 0 (TRB) : Swap of Writing Byte to AHB*/ unsigned int TRH:2; /* 3 - 2 (TRH) : Swap of Writing Half to AHB*/ unsigned int TRW:2; /* 5 - 4 (TRW) : Swap of Writing Word to AHB*/ unsigned int rs0:2; /* 7 - 6 (rs0)*/ unsigned int TTB:2; /* 9 - 8 (TTB) : Swap of Reading Byte from AHB*/ unsigned int TTH:2; /* 11 -10 (TTH) : Swap of Reading Half from AHB*/ unsigned int TTW:2; /* 13 -12 (TTW) : Swap of Reading Word from AHB*/ unsigned int rs1:2; /* 15 -14 (rs1)*/ unsigned int MRB:2; /* 17 -16 (MRB) : Swap of ARM CPU's Reading Byte*/ unsigned int MRH:2; /* 19 -18 (MRH) : Swap of ARM CPU's Reading Half*/ unsigned int MRW:2; /* 21 -20 (MRW) : Swap of ARM CPU's Reading Word*/ unsigned int rs2:2; /* 23 -22 (rs2)*/ unsigned int MTB:2; /* 25 -24 (MTB) : Swap of ARM CPU's Writing Byte*/ unsigned int MTH:2; /* 27 -26 (MTH) : Swap of ARM CPU's Writing Half*/ unsigned int MTW:2; /* 29 -28 (MTW) : Swap of ARM CPU's Writing Word*/ unsigned int rs3:2; /* 31 -30 (rs3)*/}s_PCISWAP;/* PCCARDEVT (160h) Cardbus: Socket/Function Event Register*/typedef struct /*-.-\\ Socket(host)*/{ unsigned int STC:1; /* Bit 0 (STC) : CSTSCHG(BVD[1],STSCHG#)Changed*/ unsigned int CD1:1; /* Bit 1 (CD1) : CCD#[1] Changed*/ unsigned int CD2:1; /* Bit 2 (CD2) : CCD#[2] Changed*/ unsigned int PWC:1; /* Bit 3 (PWC) : PCCARDPRS[PWC] Changed*/ unsigned int rs0:12; /* 15 - 4 (rs0)*/ unsigned int WPC:1; /* Bit 16 (WPC) : PCMCIA WP Signal Changed */ unsigned int IRC:1; /* Bit 17 (IRC) : PCMCIA READY(or IREQ#) Changed*/ unsigned int SPC:1; /* Bit 18 (SPC) : PCMCIA BVD[2](SPKR#) Changed */ unsigned int WPW:1; /* Bit 19 (WPW) : PCMCIA Memory Write But WP*/ unsigned int RDA:1; /* Bit 20 (RDA) : PCMCIA Access When Not Ready*/ unsigned int INA:1; /* Bit 21 (INA) : PCMCIA INPACK# No Ack(IO Read)*/ unsigned int rs1:10; /* 31 -22 (rs1)*/}s_PCCARDEVT;typedef struct /*-.-\\ Function(agent)*/{ unsigned int rs0:4; /* 3 - 0 (rs0)*/ unsigned int GWA:1; /* Bit 4 (GWA) : General Wakeup Event*/ unsigned int rs1:10; /* 14 - 5 (rs1)*/ unsigned int INT:1; /* Bit 15 (INT) : Function Event Interrupt Event*/ unsigned int rs2:16; /* 31 -16 (rs2)*/}f_PCCARDEVT;/* PCCARDEVM (164h) Cardbus: Socket/Function Event Mask Register*/typedef struct /*-.-\\ Socket(host)*/{ unsigned int STC:1; /* Bit 0 (STC) : PCCARDEVT[STC] Intrpt Enable*/ unsigned int CD1:1; /* Bit 1 (CD1) : PCCARDEVT[CD1] Intrpt Enable*/ unsigned int CD2:1; /* Bit 2 (CD2) : PCCARDEVT[CD2] Intrpt Enable*/ unsigned int PWC:1; /* Bit 3 (PWC) : PCCARDEVT[PWC] Intrpt Enable*/ unsigned int rs0:12; /* 15 - 4 (rs0)*/ unsigned int WPC:1; /* Bit 16 (WPC) : PCCARDEVT[WPC] Intrpt Enable */ unsigned int IRC:1; /* Bit 17 (IRC) : PCCARDEVT[IRC] Intrpt Enable */ unsigned int SPC:1; /* Bit 18 (SPC) : PCCARDEVT[SPC] Intrpt Enable */ unsigned int WPW:1; /* Bit 19 (WPW) : PCCARDEVT[WPW] Intrpt Enable */ unsigned int RDA:1; /* Bit 20 (RDA) : PCCARDEVT[RDA] Intrpt Enable */ unsigned int INA:1; /* Bit 21 (INA) : PCCARDEVT[INA] Intrpt Enable */ unsigned int rs1:10; /* 31 -22 (rs1)*/}s_PCCARDEVM;typedef struct /*-.-\\ Function(agent)*/{ unsigned int rs0:4; /* 3 - 0 (rs0)*/ unsigned int GWA:1; /* Bit 4 (GWA) : General Wakeup Event Mask*/ unsigned int rs1:9; /* 13 - 5 (rs1)*/ unsigned int WKU:1; /* Bit 14 (WKU) : Wakeup Mask to CSTSCHG Signal*/ unsigned int INT:1; /* Bit 15 (INT) : Function Event Interrupt Mask*/ unsigned int rs2:16; /* 31 -16 (rs2)*/}f_PCCARDEVM;/* PCCARDPRS (168h) Cardbus: Socket/Function Present State Register*/typedef struct /*-.-\\ Socket(host)*/{ unsigned int STC:1; /* Bit 0 (STC) : CSTSCHGorBVD[1](STSCHG#) Pin*/ unsigned int CD1:1; /* Bit 1 (CD1) : CCD#[1] Pin Status*/ unsigned int CD2:1; /* Bit 2 (CD2) : CCD#[2] Pin Status*/ unsigned int PWC:1; /* Bit 3 (PWC) : Power Up Cycle Done Status*/ unsigned int C16:1; /* Bit 4 (C16) : 16-bit PC Card Inserted*/ unsigned int C32:1; /* Bit 5 (C32) : CardBus PC Card Inserted*/ unsigned int rs0:1; /* Bit 6 (rs0)*/ unsigned int CNO:1; /* Bit 7 (CNO) : Not a card (Not Determined)*/ unsigned int DTL:1; /* Bit 8 (DTL) : Data Lost or Left in FIFO*/ unsigned int BVR:1; /* Bit 9 (BVR) : Bad Vcc Request from Software*/ unsigned int C5V:1; /* Bit 10 (C5V) : Card Activated at Vcc=5V*/ unsigned int C3V:1; /* Bit 11 (C3V) : Card Activated at Vcc=3V*/ unsigned int CXV:1; /* Bit 12 (CXV) : Card Activated at Vcc=X.X V*/ unsigned int CYV:1; /* Bit 13 (CYV) : Card Activated at Vcc=Y.Y V*/ unsigned int CVS:1; /* Bit 14 (CVS) : Now in CVS Test (Not in Spec.)*/ unsigned int rs1:1; /* Bit 15 (rs1)*/ unsigned int WPS:1; /* Bit 16 (WPS) : PCMCIA WP Signal Status*/ unsigned int RDY:1; /* Bit 17 (RDY) : PCMCIA READY(IREQ#) Signal*/ unsigned int BVD:1; /* Bit 18 (BVD) : PCMCIA BVD[2](SPKR#) Status*/ unsigned int rs2:2; /* 20- 19 (rs2)*/ unsigned int INP:1; /* Bit 21 (INP) : PCMCIA INPACK# Status*/ unsigned int rs3:6; /* 27- 22 (rs3)*/ unsigned int S5V:1; /* Bit 28 (S5V) : 1 = Socket Can Apply Vcc=5V*/ unsigned int S3V:1; /* Bit 29 (S3V) : 1 = Socket Can Apply Vcc=3V*/ unsigned int SXV:1; /* Bit 30 (SXV) : 0 = Socket NOT Apply Vcc=X.X V*/ unsigned int SYV:1; /* Bit 31 (SYV) : 0 = Socket NOT Apply Vcc=Y.Y V*/}s_PCCARDPRS;typedef struct /*-.-\\ Function(agent)*/{ unsigned int WRP:1; /* Bit 0 (WRP) : 0 = Not write protected*/ unsigned int RED:1; /* Bit 1 (RED) : 1 = Ready*/ unsigned int BVD:2; /* 3 - 2 (BVD) : 11 = Battery operational*/ unsigned int GWA:1; /* Bit 4 (GWA) : General Wakeup Event Status*/ unsigned int rs0:10; /* 14 - 5 (rs0)*/ unsigned int INT:1; /* Bit 15 (INT) : Function Event Status*/ unsigned int rs1:16; /* 31 -16 (rs1)*/}f_PCCARDPRS;/* PCCARDFEV (16Ch) Cardbus: Socket/Function Force Event Register*/typedef struct /*-.-\\ Socket(host)*/{ unsigned int STC:1; /* Bit 0 (STC) : Simulate PCCARDEVT[STC] to 1*/ unsigned int CD1:1; /* Bit 1 (CD1) : Simulate PCCARDEVT[CD1] to 1*/ unsigned int CD2:1; /* Bit 2 (CD2) : Simulate PCCARDEVT[CD2] to 1*/ unsigned int PWC:1; /* Bit 3 (PWC) : Simulate PCCARDEVT[PWC] to 1*/ unsigned int C16:1; /* Bit 4 (C16) : Simulate 16-bit Inserted*/ unsigned int C32:1; /* Bit 5 (C32) : Simulate CardBus Inserted*/ unsigned int rs0:1; /* Bit 6 (rs0)*/ unsigned int CNO:1; /* Bit 7 (CNO) : Simulate No PC Card*/ unsigned int DTL:1; /* Bit 8 (DTL) : Write PCCARDPRS[DTL]*/ unsigned int BVR:1; /* Bit 9 (BVR) : Write PCCARDPRS[BVR]*/ unsigned int C5V:1; /* Bit 10 (C5V) : Write PCCARDPRS[C5V]*/ unsigned int C3V:1; /* Bit 11 (C3V) : Write PCCARDPRS[C3V]*/ unsigned int CXV:1; /* Bit 12 (CXV) : Write PCCARDPRS[CXV]*/ unsigned int CYV:1; /* Bit 13 (CYV) : Write PCCARDPRS[CYV]*/ unsigned int CVS:1; /* Bit 14 (CVS) : CVS Test Interrogating*/ unsigned int rs1:1; /* Bit 15 (rs1) */ unsigned int SPC:1; /* Bit 16 (SPC) : Simulate PCCARDEVT[SPC] to 1*/ unsigned int IRC:1; /* Bit 17 (IRC) : Simulate PCCARDEVT[IRC] to 1*/ unsigned int WPC:1; /* Bit 18 (WPC) : Simulate PCCARDEVT[WPC] to 1*/ unsigned int RDA:1; /* Bit 19 (RDA) : Simulate PCCARDEVT[RDA] to 1*/ unsigned int WPW:1; /* Bit 20 (WPW) : Simulate PCCARDEVT[WPW] to 1*/ unsigned int INA:1; /* Bit 21 (INA) : Simulate PCCARDEVT[INA] to 1*/ unsigned int rs2:10; /* 31- 22 (rs2)*/}s_PCCARDFEV;typedef struct /*-.-\\ Function(agent)*/{ unsigned int rs0:4; /* 3 - 0 (rs0)*/ unsigned int GWA:1; /* Bit 4 (GWA) : Force Wakeup Event*/ unsigned int rs1:10; /* 14 - 5 (rs1)*/ unsigned int INT:1; /* Bit 15 (INT) : Force Function Event Interrupt*/ unsigned int rs2:16; /* 31 -16 (rs2)*/}f_PCCARDFEV;/* PCCARDCON (170h) Cardbus: Socket Control Register*/typedef struct /*-.-\\ Socket(host)*/{ unsigned int VPP:3; /* 2 - 0 (VPP) : VPP (0=off,1=12V,2=5V,3=3.3V)*/ unsigned int rs0:1; /* Bit 3 (rs0)*/ unsigned int VCC:3; /* 6 - 4 (VCC) : VCC (0=off, 2=5V, 3=3.3V)*/ unsigned int rs1:16; /* 22 - 7 (rs1)*/ unsigned int ACT:1; /* Bit 23 (ACT) : Card Signals Active*/ unsigned int CST:8; /* 31 -24 (CST) : Card State*/}s_PCCARDCON;/* PCCARD16C (174h) PCMCIA Host: Control Register*/typedef struct /*-.-\\ host*/{ unsigned int CDT:1; /* Bit 0 (CDT) : Card Type(0=MemOnly,1=I/O&Mem)*/ unsigned int rs0:2; /* 2 - 1 (rs0)*/ unsigned int BS:1; /* Bit 3 (BSP) : Byte Swapping to PCMCIA*/ unsigned int MMS:1; /* Bit 4 (MMS) : Mem Data Width(0=8bit,1=16bit)*/ unsigned int IOS:1; /* Bit 5 (IOS) : I/O Data Width(0=8bit,1=16bit)*/ unsigned int IOE:1; /* Bit 6 (IOE) : IOIS# Enable (0=use [IOS])*/ unsigned int rs1:19; /* 25 - 7 (rs1)*/ unsigned int WPS:1; /* Bit 26 (WPS) : WP(IOIS16#) Pin Signal Status*/ unsigned int INS:1; /* Bit 27 (INS) : INPACK# Pin Signal Status*/ unsigned int RDY:1; /* Bit 28 (RDY) : READY(IREQ#) Pin Status*/ unsigned int BVD:2; /* 30 -29 (BVD) : BVD[2:1](SPKR#,STSCHG#) Status*/ unsigned int C16:1; /* Bit 31 (C16) : 16-bit PC Card Is Installed*/}s_PCCARD16C;/* PCCARD16M (178h) PCMCIA Host: Memory Timing Register *//* PCCARD16I (17Ch) PCMCIA Host: I/O Timinig Register *//*************************************************************************** * PAST, PSST, PSL, PSHT Definition Timing Diagram⌨️ 快捷键说明
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