s3c2510pci_def.h

VxWorks BSP for S3C2510A

typedef struct 
{
	unsigned int	IOE:1;		/* Bit  0 (IOE) : I/O Space Decoding Enable */
	unsigned int	MME:1;		/* Bit  1 (MME) : Memory Space Decoding Enable */
	unsigned int	BME:1;		/* Bit  2 (BME) : Bus Master Enable */
	unsigned int	SCE:1;		/* Bit  3 (SCE) : Special Cycle Enable */
	unsigned int	MWI:1;		/* Bit  4 (MWI) : MemoryWrite&Invalidate Enable */
	unsigned int	VGA:1;		/* Bit  5 (VGA) : VGA Palette Snoop Enable */
	unsigned int	PEE:1;		/* Bit  6 (PEE) : Parity Error Response Enable */
	unsigned int	STC:1;		/* Bit  7 (STC) : Stepping Control Enable */
	unsigned int	SER:1;		/* Bit  8 (SER) : SERR Enable */
	unsigned int	FBE:1;		/* Bit  9 (FBE) : Fast Back-to-Back Enable */
	unsigned int	rs0:6;		/* 15 -10 (rs0) : Reserve */
	unsigned int	rs1:4;		/* 19 -16 (rs1) : Reserve */
	unsigned int	CAP:1;		/* Bit 20 (CAP) : Capabilities List */
	unsigned int	M66:1;		/* Bit 21 (M66) : 66MHz Capable */
	unsigned int	rs2:1;		/* Bit 22 (rs2)  :Reserve */
	unsigned int	FBC:1;		/* Bit 23 (FBB) : Fast Back-to-Back Capable */
	unsigned int	MPE:1;		/* Bit 24 (MPE) : Master Data Parity Error */
	unsigned int	DST:2;		/* 26 -25 (DST) : DEVSEL# Timing */
	unsigned int	STA:1;		/* Bit 27 (STA) : Signaled Target Abort bit */
	unsigned int	RTA:1;		/* Bit 28 (RTA) : Received Target Abort bit */
	unsigned int	RMA:1;		/* Bit 29 (RMA) : Received Master Abort bit */
	unsigned int	SSE:1;		/* Bit 30 (SSE) : Signaled System Error bit */
	unsigned int	DPE:1;		/* Bit 31 (DPE) : Detected Parity Error bit */
}s_PCIHSC_D;

#define PCIBUSMASTER_ENABLE (1<<2)
#define PCIMWI_ENABLE (1<<4)
#define PCIPERR_RESPONSE_ENABLE (1<<6)
#define PCISERR_ENABLE (1<<8)
#define PCISTATUS_ALL (0xff<<16)
#define	DEVSEL_FAST	0x0	/* s_PCIHSTS.DST == 00 */
#define	DEVSEL_MEDIUM	0x1	/* s_PCIHSTS.DST == 01 */
#define	DEVSEL_SLOW	0x2	/* s_PCIHSTS.DST == 10 */

/*	PCIHCODE	(008h) PCI_H : Class code, Revision ID */

typedef struct 
{
	unsigned int	REV:8;		/*  7 - 0 (REV) : Revision ID */
	unsigned int	PGI:8;		/* 15 - 8 (PGI) : Class Code - Programming I/F */
	unsigned int	SCC:8;		/* 23 -16 (SCC) : Class Code - Sub-class code */
	unsigned int	BCC:8;		/* 31 -24 (BCC) : Class Code - Base-class code */
}s_PCIHCODE;


 /*	PCIHLINE	(00Ch) PCI_H : BIST, Header, Lat_Timer, CacheLineSize */

typedef struct 
{
	unsigned int	CLS:8;		/*  7 - 0 (CLS) : Cache Line Size */
	unsigned int	LTT:8;		/* 15 - 8 (LTT) : Latency Timer */
	unsigned int	HDT:8;		/* 23 -16 (HDT) : Header Type */
	unsigned int	BIS:8;		/* 31 -24 (BIS) : BIST(Built-in Self Test) */
}s_PCIHLINE;

/*	PCIHLINE	(00Ch) PCI_H : BIST, Header, Lat_Timer, CacheLineSize */

typedef struct 
{
	unsigned int	CLS:8;		/*  7 - 0 (CLS) : Cache Line Size */
	unsigned int	LTT:8;		/* 15 - 8 (LTT) : Latency Timer */
	unsigned int	HTP:6;		/* 22 -16 (HTP) : Header Type */
	unsigned int	SMF:2;		/* Bit 23 (SMF) : Single/Multi Function */
	unsigned int	CMP:4;		/* 27 -24 (CMP) : Completion Code */
	unsigned int	rs0:2;		/* 29 -28 (rs0) */
	unsigned int	STB:1;		/* Bit 30 (STB) : Start BIST */
	unsigned int	CAP:1;		/* Bit 31 (CAP) : BIST Capable */
}s_PCIHLINE_D;

/***************************************************************************
 *					Mem Base Address Register
 *  PCIHBAR0	(010h) PCI_H : Mem Base Address Register 0
 *  PCIHBAR1	(014h) PCI_H : Mem Base Address Register 1
 *  PCIHBAR2	(018h) PCI_H : I/O  Base Address Register 2
 **************************************************************************/

typedef struct 
{
	unsigned int	IND:1;		/* Bit  0 (IND) : Space Indicator(0=Mem,1=IO) */
	unsigned int	BAR:31;		/* 31 - 1 (BAR) : Base Address Register */
}s_PCIHBAR;

/* Memory Base Address Register */

typedef struct 
{
	unsigned int	IND:1;		/* Bit  0 (IND) : Space Indicator(0=Mem) */
	unsigned int	TYP:2;		/*  2 - 1 (TYP) : Memory I/F Type */
	unsigned int	PRF:1;		/* Bit  3 (PRF) : Prefetchable */
	unsigned int	BAR:28;		/* 31 - 4 (BAR) : Base Address Register */
}s_PCIHMBAR;

/* I/O Base Address Register */

typedef struct 
{
	unsigned int	IND:1;		/* Bit  0 (IND) : Space Indicator(1=IO) */
	unsigned int	rs0:1;		/* Bit  1 (rs0) */
	unsigned int	BAR:30;		/* 31 - 2 (BAR) : Base Address Register */
}s_PCIHIBAR;

typedef struct
{
	unsigned int	ADE:1;		/* Bit  0 (ADE) : Address Decode Enable */
	unsigned int	rs0:10;		/* 10 - 1 (rs0) */
	unsigned int	BAR:21;		/* 31 -11 (BAR) : Expansion ROM Base Address */
}s_PCIHRBAR;

#define	MEM_BAR		0	/* s_PCIHBAR.IND */
#define	IO_BAR		1	/* s_PCIHBAR.IND */

#define	MEM_TYPE_32	0	/* s_PCIHMBAR.TYP : in 32bit address (4G) region */
#define	MEM_TYPE_20	1	/* s_PCIHMBAR.TYP : not PCI2.2 but CardBus */
#define	MEM_TYPE_64	2	/* s_PCIHMBAR.TYP : in 64bit address region */


/*	PCIHCISP	(028h) PCI_H : CIS(CardBusInformationStructure) Pointer */

typedef struct 
{
	unsigned int	IND:3;		/*  2 - 0 (IND) : Address Space Indicator */
	unsigned int	OFF:29;		/* 31 - 3 (OFF) : Address Space Offset(ROM Img) */
}s_PCIHCISP;

#define	CIS_IN_CFG	0	/* s_PCIHCISP.IND : Configuration Space */
#define	CIS_IN_BAR0	1	/* s_PCIHCISP.IND : BAR0 (10h) */
#define	CIS_IN_BAR1	2	/* s_PCIHCISP.IND : BAR1 (14h) */
#define	CIS_IN_BAR2	3	/* s_PCIHCISP.IND : BAR2 (18h) */
#define	CIS_IN_BAR3	4	/* s_PCIHCISP.IND : BAR3 (1Ch) */
#define	CIS_IN_BAR4	5	/* s_PCIHCISP.IND : BAR4 (20h) */
#define	CIS_IN_BAR5	6	/* s_PCIHCISP.IND : BAR5 (24h) */
#define	CIS_IN_EXPR	7	/* s_PCIHCISP.IND : Expansion Rom (30h) */

/*	PCIHSSID	(02Ch) PCI_H : SubSystem ID, SubSystem Vendor ID */

typedef struct 
{
	unsigned int	SVD:16;		/* 15 - 0 (SVD) : SubSystem Vendor ID */
	unsigned int	SID:16;		/* 31 -16 (SID) : SubSystem ID */
}s_PCIHSSID;

/*	PCIHCAP		(034h) PCI_H : Capabilities List Pointer */

typedef struct 
{
	unsigned int	CAP:8;		/*  7 - 0 (CAP) : Capabilities Pointer */
	unsigned int	rs0:24;		/* 31 - 8 (rs0) */
}s_PCIHCAP;


/*	PCIHLTIT	(03Ch) PCI_H : Max_Lat, Min_Gnt, Int_Pin, Int_Line */

typedef struct 
{
	unsigned int	INL:8;		/*  7 - 0 (INL) : Int_Line(0=IRQ0,1=IRQ1,255=no) */
	unsigned int	INP:8;		/* 15 - 8 (INP) : Int_Pin(0=no,1=INTA#,2=INTB#) */
	unsigned int	MGT:8;		/* 23 -16 (MGT) : Min_Gnt(How long occupy bus) */
	unsigned int	MLT:8;		/* 31 -24 (MLT) : Max_Lat(How much request bus) */
}s_PCIHLTIT;


/*	PCIHTIMER	(040h) PCI_H : Master Timer Register */

typedef struct 
{
	unsigned int	TRT:8;		/*  7 - 0 (TRT) : Master TRDY# Wait Timer */
	unsigned int	RTC:8;		/* 15 - 8 (RTC) : Master Retry Counter */
	unsigned int	rs0:16;		/* 31 -16 (rs0) */
}s_PCIHTIMER;


/*	PCIHPMR0	(0DCh) PCI_H : Power Management Register 0 (PMC) */

typedef struct 
{
	unsigned int	CID:8;		/*  7 - 0 (CID) : Capability ID (1=PowerMngReg) */
	unsigned int	NIP:8;		/* 15 - 8 (NIP) : Next Item Pointer */
	unsigned int	PMC:16;		/* 31 -16 (PMC) : Power Management Capabilities */
}s_PCIHPMR0;

/*	PCIHPMR0	(0DCh) PCI_H : Power Management Register 0 (PMC) */

typedef struct 
{
	unsigned int	CID:8;		/*  7 - 0 (CID) : Capability ID (1=PowerMngReg) */ 
	unsigned int	NIP:8;		/* 15 - 8 (NIP) : Next Item Pointer */
	unsigned int	VER:3;		/* 18 -16 (VER) : Power Mng I/F Spec. Version */
	unsigned int	CLK:1;		/* Bit 19 (CLK) : PCI Clock Necessity for PME# */
	unsigned int	rs0:1;		/* Bit 20 (rs0) */
	unsigned int	DSI:1;		/* Bit 21 (DSI) : Device Specific Initial. */
	unsigned int	AUX:3;		/* 24 -22 (AUX) : Aux Current */
	unsigned int	D1S:1;		/* Bit 25 (D1S) : D1 State Support */
	unsigned int	D2S:1;		/* Bit 26 (D2S) : D2 State Support */
	unsigned int	PD0:1;		/* Bit 27 (PD0) : PME# Support from D0 */
	unsigned int	PD1:1;		/* Bit 28 (PD1) : PME# Support from D1 */
	unsigned int	PD2:1;		/* Bit 29 (PD2) : PME# Support from D2 */
	unsigned int	PD3:1;		/* Bit 30 (PD3) : PME# Support from D3hot */
	unsigned int	PDC:1;		/* Bit 31 (PDC) : PME# Support from D3cold */
}s_PCIHPMR0_D;

#define	AUX_375mA	7		/* s_PCIHPMR0_D.AUX : 3.3Vaux Max Current */
#define	AUX_320mA	6		/* s_PCIHPMR0_D.AUX : 3.3Vaux Max Current */
#define	AUX_270mA	5		/* s_PCIHPMR0_D.AUX : 3.3Vaux Max Current */
#define	AUX_220mA	4		/* s_PCIHPMR0_D.AUX : 3.3Vaux Max Current */
#define	AUX_160mA	3		/* s_PCIHPMR0_D.AUX : 3.3Vaux Max Current */
#define	AUX_100mA	2		/* s_PCIHPMR0_D.AUX : 3.3Vaux Max Current */
#define	AUX_55mA	1		/* s_PCIHPMR0_D.AUX : 3.3Vaux Max Current */
#define	AUX_SelfPower	0	/* s_PCIHPMR0_D.AUX : 3.3Vaux Max Current */


/*	PCIHPMR1	(0E0h) PCI_H : Power Management Register 1 (PMCSR) */

typedef struct 
{
	unsigned int	CSR:16;		/* 15 - 0 (CSR) : PMCSR (Control/Status Reg) */
	unsigned int	BSE:8;		/* 23 -16 (BSE) : PMCSR_BSE(Bridge Support Ext) */
	unsigned int	DAT:8;		/* 31 -24 (DAT) : Data Register */
}s_PCIHPMR1;

/*	PCIHPMR1	(0E0h) PCI_H : Power Management Register 1 (PMCSR) */

typedef struct 
{
	unsigned int	PST:2;		/*  1 - 0 (PST) : Power State */
	unsigned int	rs0:6;		/*  7 - 2 (rs0) */
	unsigned int	PME:1;		/* Bit  8 (PME) : PME_Enable bit */
	unsigned int	DSL:4;		/* 12 - 9 (DSL) : Data Register Select */
	unsigned int	DSC:2;		/* 14 -13 (DSC) : Data Register Scale */
	unsigned int	PMS:1;		/* Bit 15 (PMS) : PME_Status bit */
	unsigned int	rs1:6;		/* 21 -16 (rs1) */
	unsigned int	B23:1;		/* Bit 22 (B23) : B2_B3# support for D3hot */
	unsigned int	BPE:1;		/* Bit 23 (BPE) : BPCC_En (Bus Power/Clock Con) */
	unsigned int	DAT:8;		/* 31 -24 (DAT) : Data Register */
}s_PCIHPMR1_D;

#define	PMSTATE_D0	0	/* s_PCIHPMR1_D.PST == 0 */
#define	PMSTATE_D1	1	/* s_PCIHPMR1_D.PST == 1 */
#define	PMSTATE_D2	2	/* s_PCIHPMR1_D.PST == 2 */
#define	PMSTATE_D3	3	/* s_PCIHPMR1_D.PST == 3 : D3hot */


/*	PCICON		(100h) PCI Control & Status Register */

typedef struct 
{
	unsigned int	HST:1;		/* Bit  0 (HST) : Host Mode */
	unsigned int	ARB:1;		/* Bit  1 (ARB) : Internal PCI Arbiter Enable */
	unsigned int	rs0:2;		/*  3 - 2 (rs0) */
	unsigned int	ATS:1;		/* Bit  4 (ATS) : Address Translation to PCI */
	unsigned int	SPL:1;		/* Bit  5 (SPL) : Split Response Mode */
	unsigned int	IOP:1;		/* Bit  6 (IOP) : PCI I/O Space Prefetchable */
	unsigned int	MMP:1;		/* Bit  7 (MMP) : PCI Memory Space Prefetchable */
	unsigned int	CFD:1;		/* Bit  8 (CFD) : Configuration Done */
	unsigned int	RDY:1;		/* Bit  9 (RDY) : PCI Target Ready to Read */
	unsigned int	rs1:6;		/* 15 -10 (rs1) */
	unsigned int	WKI:1;		/* Bit 16 (WKI): PME# Assert by ARM interrupt */
	unsigned int	WKA:1;		/* Bit 17 (WKA) : PME_Status(PME#) Assert */
	unsigned int	rs2:6;		/* 23 -18 (rs2) */
	unsigned int	CAR:1;		/* Bit 24 (CAR) : Cardbus Interface Mode */
	unsigned int	rs3:3;		/* 27 -25 (rs3) */
	unsigned int	TBS:1;		/* Bit 28 (TBS) : PCI Target Busy */
	unsigned int	MBS:1;		/* Bit 29 (MBS) : PCI Master Busy */
	unsigned int	DBS:1;		/* Bit 30 (DBS) : PCI DMA Busy */
	unsigned int	INT:1;		/* Bit 31 (INT) : Internal Interrupt Signaled  */
}s_PCICON;

#define PCIARBITOR_INT (1<<1)
#define PCIARBITOR_EXT (~PCIARBITOR_INT)
#define PCICONFIG_DONE (1<<8)
#define PCISYSTEMREAD_READY (1<<9)


/*	PCISET		(104h) PCI Command, Read Count & DAC Address Register*/

typedef struct 
{
	unsigned int	DAC:8;		/*  7 - 0 (DAC) : DAC Upper 8 Bit Address */
	unsigned int	RDC:8;		/* 15 - 8 (RDC) : Read Word Count */
	unsigned int	CMD:4;		/* 19 -17 (CMD) : PCI Command if PCICON[ATS]=0 */
	unsigned int	rs0:12;		/* 31 -20 (rs0) */
}s_PCISET;


/*	PCIINTEN	(108h) PCI Interrupt Enable Register*/

typedef struct 
{
	unsigned int	PRD:1;		/* Bit  0 (PRD) : Enable of PCIINTST[PRD]*/
	unsigned int	PRA:1;		/* Bit  1 (PRA) : Enable of PCIINTST[PRA]*/
	unsigned int	MFE:1;		/* Bit  2 (MFE) : Enable of PCIINTST[MFE]*/
	unsigned int	MPE:1;		/* Bit  3 (MPE) : Enable of PCIINTST[MPE]*/
	unsigned int	TPE:1;		/* Bit  4 (TPE) : Enable of PCIINTST[TPE]*/
	unsigned int	PME:1;		/* Bit  5 (PME) : Enable of PCIINTST[PME]*/
	unsigned int	PMC:1;		/* Bit  6 (PMC) : Enable of PCIINTST[PMC]*/
	unsigned int	PSC:1;		/* Bit  7 (PSC) : Enable of PCIINTST[PSC]*/
	unsigned int	BPA:1;		/* Bit  8 (BPA) : Enable of PCIBELPA[BEL]*/
	unsigned int	SER:1;		/* Bit  9 (SER) : Enable of PCIINTST[SER]*/
	unsigned int	INA:1;		/* Bit 10 (INA) : Enable of PCIINTST[INA]*/
	unsigned int	rs0:1;		/* Bit 11 (rs0)*/
	unsigned int	DM0:1;		/* Bit 12 (DM0) : Enable of PCIINTST[DM0]*/
	unsigned int	DE0:1;		/* Bit 13 (DE0) : Enable of PCIINTST[DE0]*/
	unsigned int	DM1:1;		/* Bit 14 (DM1) : Enable of PCIINTST[DM1]*/
	unsigned int	DE1:1;		/* Bit 15 (DE1) : Enable of PCIINTST[DE1]*/
	unsigned int	AER:1;		/* Bit 16 (AER) : Enable of PCIINTST[AER]*/
	unsigned int	rs1:14;		/* 30 -17 (rs1)*/
	unsigned int	BAP:1;		/* Bit 31 (BAP) : Enable of PCIBELAP[BEL]*/
}s_PCIINTEN;


/*	PCIINTST	(10Ch) PCI Interrupt Status Register*/

typedef struct 
{
	unsigned int	PRD:1;		/* Bit  0 (PRD) : PCI Reset Deasserted*/
	unsigned int	PRA:1;		/* Bit  1 (PRA) : PCI Reset Asserted*/
	unsigned int	MFE:1;		/* Bit  2 (MFE) : PCI Master Fatal Error*/
	unsigned int	MPE:1;		/* Bit  3 (MPE) : PCI Master Parity Error*/
	unsigned int	TPE:1;		/* Bit  4 (TPE) : PCI Target Parity Error*/
	unsigned int	PME:1;		/* Bit  5 (PME) : PME Enable Asserted or PME#*/
	unsigned int	PMC:1;		/* Bit  6 (PMC) : PME Clear  Asserted*/