s3c2510pci_def.h

VxWorks BSP for S3C2510A

/*************************************************************************
*                                                                       
* FILE NAME:                                                             
*     s3c2510Pci_def.h                                        		 
*                                                                       
* DESCRIPTION: 
* SAMSUNG S3C2510 PCI function register definitions.
* The file defines the PCI function register definitions, their offset and base address.      
*   
*                                                         
*                   
*                                                                       
*-----------------------------------------------------------------------
* Copyright (C) 2003 Samsung Electronics. Inc., SISO, Bangalore             
*-----------------------------------------------------------------------
*  
* History
* -------                                                                                                                                   
* NAME            DATE              Modification Note
* 
* Sachin Prasad    08 Jul  2003        Modified to make Ansi C compliant
* WG, Kim           Jan 2003 		 Created	
*                                                                       
*************************************************************************/

#ifndef _S3C2510PCI_DEF_H_ /* Include file once */
#define _S3C2510PCI_DEF_H_


/* typedefs */

typedef unsigned long	u32;
typedef unsigned short	u16;
typedef unsigned char	u8;

/* Definition for PC Card Standard */
/* PCCARDCON[VPP, VCC]  */
#define	VCCPP_OFF	0	/* 3'b000 = Power off */
#define	VCCPP_12V	1	/* 3'b001 = 12V (only VPP) */
#define	VCCPP_5V	2	/* 3'b010 = 5V */
#define	VCCPP_3_3V	3	/* 3'b011 = 3.3V */
#define	VCCPP_X_XV	4	/* 3'b100 = X.XV */
#define	VCCPP_Y_YV	5	/* 3'b101 = Y.YV */

/* Macro Definitions */
#define	r32(addr)	(*(volatile unsigned long*)(addr))
#define	r16(addr)	(*(volatile unsigned short*)(addr))
#define	r8(addr)	(*(volatile unsigned char* )(addr))

/* co: Code Optimization */
#define	co_r32(addr)	(*(unsigned long*)(addr))
#define	co_r16(addr)	(*(unsigned short*)(addr))
#define	co_r8(addr)	    (*(unsigned char* )(addr))

/* Declarations for PCI SFR (Address) */
#define	MEM_OFF		0x00000000	/* bit [28:0] */
#define	CFG0_OFF	0x10000000
#define	CFG1_OFF	0x14000000
#define	SPEC_OFF	0x18000000
#define	IO_OFF		0x1C000000

#define	BIF_OFF		0x100		/* bit [8:0] */
#define	PDMA0_OFF	0x180
#define	PDMA1_OFF	0x1A0
#define	PDMACH_OFF	0x020		/* (PDMA1_OFF-PDMA0_OFF) */

#define	PCIHID_OFF	0x00
#define	PCIHVID_OFF 0x00
#define	PCIHDID_OFF 0x02
#define	PCIHSC_OFF	0x04
#define	PCIHCMD_OFF	0x04
#define	PCIHST_OFF	0x06
#define	PCIHCODE_OFF	0x8
#define	PCIHREV_OFF	0x08
#define	PCIHCLASS_OFF	0x09
#define	PCIHLINE_OFF	0x0C
#define	PCIHLATTIMER_OFF	0x0d
#define	PCIHHEADER_OFF 0x0e
#define	PCIHBIST_OFF	0x0f
#define	PCIHBAR0_OFF	0x10
#define	PCIHBAR1_OFF	0x14
#define	PCIHBAR2_OFF	0x18
#define	PCIHBAR3_OFF	0x1C
#define	PCIHBAR4_OFF	0x20
#define	PCIHBAR5_OFF	0x24
#define	PCIHCISP_OFF	0x28
#define	PCIHSSID_OFF	0x2C
#define	PCIHSSVID_OFF	0x2e
#define	PCIHEXPR_OFF	0x30	/* reserved region */
#define	PCIHCAP_OFF	0x34
#define	PCIHLTIT_OFF	0x3C
#define	PCIHINTLINE_OFF	0x3c
#define	PCIHINTPIN_OFF	0x3D
#define	PCIHMINGNT_OFF	0x3E
#define	PCIHMAXLAT_OFF	0x3F
#define	PCIHTIMER_OFF	0x40
#define	PCIHPMR0_OFF	0xDC
#define	PCIHPMR1_OFF	0xE0

#define	PCICON_OFF	0x00
#define	PCISET_OFF	0x04
#define	PCIINTEN_OFF	0x08
#define	PCIINTST_OFF	0x0C
#define	PCIINTAD_OFF	0x10
#define	PCIBATAPM_OFF	0x14
#define	PCIBATAPI_OFF	0x18
#define	PCIRCC_OFF	0x1C
#define	PCIDIAG0_OFF	0x20
#define	PCIDIAG1_OFF	0x24
#define	PCIBELAP_OFF	0x28
#define	PCIBELPA_OFF	0x2C
#define	PCIMAIL0_OFF	0x30
#define	PCIMAIL1_OFF	0x34
#define	PCIMAIL2_OFF	0x38
#define	PCIMAIL3_OFF	0x3C
#define	PCIBATPA0_OFF	0x40
#define	PCIBAM0_OFF	0x44
#define	PCIBATPA1_OFF	0x48
#define	PCIBAM1_OFF	0x4C
#define	PCIBATPA2_OFF	0x50
#define	PCIBAM2_OFF	0x54
#define	PCISWAP_OFF	0x58
#define	PCCARDEVT_OFF	0x60
#define	PCCARDEVM_OFF	0x64
#define	PCCARDPRS_OFF	0x68
#define	PCCARDFEV_OFF	0x6C
#define	PCCARDCON_OFF	0x70
#define	PCCARD16C_OFF	0x74
#define	PCCARD16M_OFF	0x78
#define	PCCARD16I_OFF	0x7C

#define	PDMACON_OFF	0x00
#define	PDMASRC_OFF	0x04
#define	PDMADST_OFF	0x08
#define	PDMACNT_OFF	0x0C
#define	PDMARUN_OFF	0x10

/* PCMCIA(16-bit PC Card) Host AHB Address Offsets */
#define	PCMCIAAM_OFF	0x00000000	
#define	PCMCIACM_OFF	0x04000000	
#define	PCMCIAIO_OFF	0x08000000	


/* Real Address (AHB or PCI or PCMCIA) */
#define	BS_FIELD 	0xe0000000	/*refer to User's Manual */
#define	CS 	0x1c000000	/*refer to User's Manual */
#define	PCI_ADDR	0xC0000000 /* Address Space as Master */
#define	PCISFR_ADDR	0xF0110000 /* Special Register Space */
#define	PCIMEM_ADDR		( PCI_ADDR	+ MEM_OFF	)
#define	PCICFG0_ADDR	( PCI_ADDR	+ CFG0_OFF	)
#define	PCICFG1_ADDR	( PCI_ADDR	+ CFG1_OFF	)
#define	PCISPEC_ADDR	( PCI_ADDR	+ SPEC_OFF	)
#define	PCIIO_ADDR		( PCI_ADDR	+ IO_OFF	)
#define	PCMCIAAM_ADDR	( PCI_ADDR	+ PCMCIAAM_OFF	)
#define	PCMCIACM_ADDR	( PCI_ADDR	+ PCMCIACM_OFF	)
#define	PCMCIAIO_ADDR	( PCI_ADDR	+ PCMCIAIO_OFF	)
#define	BIFSFR_ADDR		( PCISFR_ADDR	+ BIF_OFF	)
#define	PDMA0SFR_ADDR	( PCISFR_ADDR	+ PDMA0_OFF	)
#define	PDMA1SFR_ADDR	( PCISFR_ADDR	+ PDMA1_OFF	)

#define	PCIHID		( PCISFR_ADDR	+ PCIHID_OFF	)
#define	PCIHSC		( PCISFR_ADDR	+ PCIHSC_OFF	)
#define	PCIHCODE	( PCISFR_ADDR	+ PCIHCODE_OFF	)
#define	PCIHLINE	( PCISFR_ADDR	+ PCIHLINE_OFF	)
#define	PCIHBAR0	( PCISFR_ADDR	+ PCIHBAR0_OFF	)
#define	PCIHBAR1	( PCISFR_ADDR	+ PCIHBAR1_OFF	)
#define	PCIHBAR2	( PCISFR_ADDR	+ PCIHBAR2_OFF	)
#define	PCIHCISP	( PCISFR_ADDR	+ PCIHCISP_OFF	)
#define	PCIHSSID	( PCISFR_ADDR	+ PCIHSSID_OFF	)
#define	PCIHCAP		( PCISFR_ADDR	+ PCIHCAP_OFF	)
#define	PCIHLTIT	( PCISFR_ADDR	+ PCIHLTIT_OFF	)
#define	PCIHTIMER	( PCISFR_ADDR	+ PCIHTIMER_OFF	)
#define	PCIHPMR0	( PCISFR_ADDR	+ PCIHPMR0_OFF	)
#define	PCIHPMR1	( PCISFR_ADDR	+ PCIHPMR1_OFF	)

#define	PCICON		( BIFSFR_ADDR	+ PCICON_OFF	)
#define	PCISET		( BIFSFR_ADDR	+ PCISET_OFF	)
#define	PCIINTEN	( BIFSFR_ADDR	+ PCIINTEN_OFF	)
#define	PCIINTST	( BIFSFR_ADDR	+ PCIINTST_OFF	)
#define	PCIINTAD	( BIFSFR_ADDR	+ PCIINTAD_OFF	)
#define	PCIBATAPM	( BIFSFR_ADDR	+ PCIBATAPM_OFF	)
#define	PCIBATAPI	( BIFSFR_ADDR	+ PCIBATAPI_OFF	)
#define	PCIRCC		( BIFSFR_ADDR	+ PCIRCC_OFF	)
#define	PCIDIAG0	( BIFSFR_ADDR	+ PCIDIAG0_OFF	)
#define	PCIDIAG1	( BIFSFR_ADDR	+ PCIDIAG1_OFF	)
#define	PCIBELAP	( BIFSFR_ADDR	+ PCIBELAP_OFF	)
#define	PCIBELPA	( BIFSFR_ADDR	+ PCIBELPA_OFF	)
#define	PCIMAIL0	( BIFSFR_ADDR	+ PCIMAIL0_OFF	)
#define	PCIMAIL1	( BIFSFR_ADDR	+ PCIMAIL1_OFF	)
#define	PCIMAIL2	( BIFSFR_ADDR	+ PCIMAIL2_OFF	)
#define	PCIMAIL3	( BIFSFR_ADDR	+ PCIMAIL3_OFF	)
#define	PCIBATPA0	( BIFSFR_ADDR	+ PCIBATPA0_OFF	)
#define	PCIBAM0 	( BIFSFR_ADDR	+ PCIBAM0_OFF	)
#define	PCIBATPA1	( BIFSFR_ADDR	+ PCIBATPA1_OFF	)
#define	PCIBAM1 	( BIFSFR_ADDR	+ PCIBAM1_OFF	)
#define	PCIBATPA2	( BIFSFR_ADDR	+ PCIBATPA2_OFF	)
#define	PCIBAM2 	( BIFSFR_ADDR	+ PCIBAM2_OFF	)
#define	PCISWAP 	( BIFSFR_ADDR	+ PCISWAP_OFF	)
#define	PCCARDEVT	( BIFSFR_ADDR	+ PCCARDEVT_OFF	)
#define	PCCARDEVM	( BIFSFR_ADDR	+ PCCARDEVM_OFF	)
#define	PCCARDPRS	( BIFSFR_ADDR	+ PCCARDPRS_OFF	)
#define	PCCARDFEV	( BIFSFR_ADDR	+ PCCARDFEV_OFF	)
#define	PCCARDCON	( BIFSFR_ADDR	+ PCCARDCON_OFF	)
#define	PCCARD16C	( BIFSFR_ADDR	+ PCCARD16C_OFF	)
#define	PCCARD16M	( BIFSFR_ADDR	+ PCCARD16M_OFF	)
#define	PCCARD16I	( BIFSFR_ADDR	+ PCCARD16I_OFF	)

#define	PDMACON0	( PDMA0SFR_ADDR	+ PDMACON_OFF	)
#define	PDMASRC0	( PDMA0SFR_ADDR	+ PDMASRC_OFF	)
#define	PDMADST0	( PDMA0SFR_ADDR	+ PDMADST_OFF	)
#define	PDMACNT0	( PDMA0SFR_ADDR	+ PDMACNT_OFF	)
#define	PDMARUN0	( PDMA0SFR_ADDR	+ PDMARUN_OFF	)
#define	PDMACON1	( PDMA1SFR_ADDR	+ PDMACON_OFF	)
#define	PDMASRC1	( PDMA1SFR_ADDR	+ PDMASRC_OFF	)
#define	PDMADST1	( PDMA1SFR_ADDR	+ PDMADST_OFF	)
#define	PDMACNT1	( PDMA1SFR_ADDR	+ PDMACNT_OFF	)
#define	PDMARUN1	( PDMA1SFR_ADDR	+ PDMARUN_OFF	)

#define	PDMACON(ch)	( PDMACON0 + PDMACH_OFF*(ch)	)
#define	PDMASRC(ch)	( PDMASRC0 + PDMACH_OFF*(ch)	)
#define	PDMADST(ch)	( PDMADST0 + PDMACH_OFF*(ch)	)
#define	PDMACNT(ch)	( PDMACNT0 + PDMACH_OFF*(ch)	)
#define	PDMARUN(ch)	( PDMARUN0 + PDMACH_OFF*(ch)	)


/********************************************************************************
*					Declarations for PCI SFR (Register)                         
********************************************************************************/
#define	rPCIHID		r32( PCIHID		) /*00h Cfg Reg: Device ID, Vendor ID */
#define	rPCIHSC		r32( PCIHSC		) /*04h Cfg Reg: Status, Command */
#define	rPCIHCODE	r32( PCIHCODE	) /*08h Cfg Reg: Class code, Rev */
#define	rPCIHLINE	r32( PCIHLINE	) /*0Ch Cfg Reg: Header, Lat, CacheLine */
#define	rPCIHBAR0	r32( PCIHBAR0	) /*10h Cfg Reg: Mem base address 0 */
#define	rPCIHBAR1	r32( PCIHBAR1	) /*14h Cfg Reg: Mem base address 1 */
#define	rPCIHBAR2	r32( PCIHBAR2	) /*18h Cfg Reg: I/O base address */
#define	rPCIHCISP	r32( PCIHCISP	) /*28h Cfg Reg: CIS Pointer */
#define	rPCIHSSID	r32( PCIHSSID	) /*2Ch Cfg Reg: SSID, SVID */
#define	rPCIHCAP	r32( PCIHCAP	) /*34h Cfg Reg: Capability List */
#define	rPCIHLTIT	r32( PCIHLTIT	) /*3Ch Cfg Reg: Lat,IntPin,IntLine */
#define	rPCIHTIMER	r32( PCIHTIMER	) /*40h Cfg Reg: Master Timer */
#define	rPCIHPMR0	r32( PCIHPMR0	) /*DCh Cfg Reg: PMR0 (PMC) */
#define	rPCIHPMR1	r32( PCIHPMR1	) /*E0h Cfg Reg: PMR1 (PMCSR) */

#define	rPCIHCMD	r16( PCIHSC		) /*04h Cfg Reg: Command */
#define	rPCIHSTS	r16( PCIHSC + 2	) /*06h Cfg Reg: Status */
#define	rPCIHHDTYPE	r8 ( PCIHLINE+2	) /*0Eh Cfg Reg: Header Type */
#define	rPCIHBIST	r8 ( PCIHLINE+3	) /*0Fh Cfg Reg: BIST */
#define	rPCIHPMC	r16( PCIHPMR0+2	) /*DEh Cfg Reg: PMC */
#define	rPCIHPMCSR	r16( PCIHPMR1	) /*E0h Cfg Reg: PMCSR */
#define	rPCIHPMBSE	r8 ( PCIHPMR1+2	) /*E2h Cfg Reg: PMCSR_BSE */

#define	rPCICON		r32( PCICON		) /*100 Control & Status Register */
#define	rPCISET		r32( PCISET		) /*104 Command,Read Count & DAC Addr */
#define	rPCIINTEN	r32( PCIINTEN	) /*108 Interrupt Enable Register */
#define	rPCIINTST	r32( PCIINTST	) /*10C Interrupt Status Register */
#define	rPCIINTAD	r32( PCIINTAD	) /*110 Interrupted Address Register */
#define	rPCIBATAPM	r32( PCIBATAPM	) /*114 Base Address to PCI bus (Mem) */
#define	rPCIBATAPI	r32( PCIBATAPI	) /*118 Base Address to PCI bus (I/O) */
#define	rPCIRCC		r32( PCIRCC		) /*11C Host Mode Reset & Clock Control */
#define	rPCIDIAG0	r32( PCIDIAG0	) /*120 Diagnostic Register 0 */
#define	rPCIDIAG1	r32( PCIDIAG1	) /*124 Diagnostic Register 1 */
#define	rPCIBELAP	r32( PCIBELAP	) /*128 Doorbell Register to PCI bus */
#define	rPCIBELPA	r32( PCIBELPA	) /*12C Doorbell Register to AHB bus */
#define	rPCIMAIL0	r32( PCIMAIL0	) /*130 Mailbox Register 0 */
#define	rPCIMAIL1	r32( PCIMAIL1	) /*134 Mailbox Register 1 */
#define	rPCIMAIL2	r32( PCIMAIL2	) /*138 Mailbox Register 2 */
#define	rPCIMAIL3	r32( PCIMAIL3	) /*13C Mailbox Register 3 */
#define	rPCIBATPA0	r32( PCIBATPA0	) /*140 Base Address (Memory BAR 0) */
#define	rPCIBAM0 	r32( PCIBAM0	) /*144 Base Address BAR Mask 0 */
#define	rPCIBATPA1	r32( PCIBATPA1	) /*148 Base Address (Memory BAR 1) */
#define	rPCIBAM1 	r32( PCIBAM1	) /*14C Base Address BAR Mask 1 */
#define	rPCIBATPA2	r32( PCIBATPA2	) /*150 Base Address (I/O BAR 2) */
#define	rPCIBAM2 	r32( PCIBAM2	) /*154 Base Address BAR Mask 2 */
#define	rPCISWAP 	r32( PCISWAP	) /*158 Byte Swap Register */
#define	rPCCARDEVT	r32( PCCARDEVT	) /*160 Cardbus: Event Register */
#define	rPCCARDEVM	r32( PCCARDEVM	) /*164 Cardbus: Event Mask Register */
#define	rPCCARDPRS	r32( PCCARDPRS	) /*168 Cardbus: Present State Register */
#define	rPCCARDFEV	r32( PCCARDFEV	) /*16C Cardbus: Force Event Register */
#define	rPCCARDCON	r32( PCCARDCON	) /*170 Cardbus: Socket Control Register */
#define	rPCCARD16C	r32( PCCARD16C	) /*174 16-bit Host: Control Register */
#define	rPCCARD16M	r32( PCCARD16M	) /*178 16-bit Host: Mem Timing Register */
#define	rPCCARD16I	r32( PCCARD16I	) /*17C 16-bit Host: I/O Timing Register */

#define	rPDMACON0	r32( PDMACON0	) /*180 PMDA CH0 Control & Status */
#define	rPDMASRC0	r32( PDMASRC0	) /*184 PDMA CH0 Source Address */
#define	rPDMADST0	r32( PDMADST0	) /*188 PDMA CH0 Destination Address */
#define	rPDMACNT0	r32( PDMACNT0	) /*18C PDMA CH0 Transfer Byte Count */
#define	rPDMARUN0	r32( PDMARUN0	) /*190 PDMA CH0 Run Enable Alias */
#define	rPDMACON1	r32( PDMACON1	) /*1A0 PMDA CH1 Control & Status */
#define	rPDMASRC1	r32( PDMASRC1	) /*1A4 PDMA CH1 Source Address */
#define	rPDMADST1	r32( PDMADST1	) /*1A8 PDMA CH1 Destination Address */
#define	rPDMACNT1	r32( PDMACNT1	) /*1AC PDMA CH1 Transfer Byte Count */
#define	rPDMARUN1	r32( PDMARUN1	) /*1B0 PDMA CH1 Run Enable Alias */

#define	rPDMACON(ch)	r32( PDMACON(ch) ) 
#define	rPDMASRC(ch)	r32( PDMASRC(ch) )
#define	rPDMADST(ch)	r32( PDMADST(ch) )
#define	rPDMACNT(ch)	r32( PDMACNT(ch) )
#define	rPDMARUN(ch)	r32( PDMARUN(ch) )

/***************************************************************************
 *					PCI SFR Bit Descriptions Declarations 
 **************************************************************************/


 /* PCIHID  (000h) PCI_H : Vendor ID & Device ID */

typedef struct
{
	unsigned int	VID:16;		/* 15 - 0 (VID) : Vendor ID */
	unsigned int	DID:16;		/* 31 -16 (DID) : Device ID */
}s_PCIHID;


/*	PCIHSC		(004h) PCI_H : Status & Command Register */

typedef struct 
{
	unsigned int	CMD:16;		/* 15 - 0 (CMD) : Command (Device Control) Reg */
	unsigned int	STS:16;		/* 31 -16 (STS) : (Device) Status Register */
}s_PCIHSC;

/*	PCIHSC		(004h) PCI_H : Status & Command Register */