at91timer.h

VxWorks BSP for AT91RM92

/* at91Timer.h - Atmel AT91 timer header */

/* Copyright 2004 Wind River Systems, Inc. */
/* Copyright 1999 ARM Limited */

/*
modification history
--------------------
01b,14sep04,pdr  adapted for AT91RM9200.
01a,25jun99,jpd	 written.
*/

#ifndef	__INCat91Timerh
#define	__INCat91Timerh

#ifdef __cplusplus
extern "C" {
#endif

/* Bit definitions within registers  */

/* Timer Channel Control Register */

#define AT91_TIMER_CCR_CLKEN	(1<<0)		/* Enable Command */
#define AT91_TIMER_CCR_CLKDIS	(1<<1)		/* Disable Command */
#define AT91_TIMER_CCR_SWTRG	(1<<2)		/* Software Trigger Command */

/* Timer Channel Mode Register */

#define AT91_TIMER_CMR_MCKI_128	(3 << 0)	/* T/C fed by MCKI/128 */
#define AT91_TIMER_CMR_CPCTRG	(1 << 14)	/* Trigger on reg C compare */
#define AT91_TIMER_CMR_WAVE	    (1 << 15)	/* Trigger on reg C compare */

/* Interrupt Enable Register */

#define AT91_TIMER_IER_CPCS	    (1 << 4)	/* Interrupt on reg C compare */

/* timer base address */

#ifndef AT91_TIMER_BASE
#define AT91_TIMER_BASE		    0xFFFA0000	/* Base adrs of timers */
#endif


/* Register definitions */

#define AT91_TIMER_0	0	/* timer block numbers */
#define AT91_TIMER_1	1
#define AT91_TIMER_2	2

#define AT91_TIMER_BLOCK_OFFSET	0x40	/* byte offset between timer blocks */

#ifndef SYS_TIMER_NUM
#define SYS_TIMER_NUM	AT91_TIMER_0	/* default the sys timer to timer 0 */
#endif
#ifndef AUX_TIMER_NUM
#define AUX_TIMER_NUM	AT91_TIMER_1	/* default the aux timer to timer 1 */
#endif

#define SYS_TIMER_BASE \
	((AT91_TIMER_BASE) + ((SYS_TIMER_NUM) * AT91_TIMER_BLOCK_OFFSET))
#define AUX_TIMER_BASE \
	((AT91_TIMER_BASE) + ((AUX_TIMER_NUM) * AT91_TIMER_BLOCK_OFFSET))

/* Register address definitions */

#define SYS_TIMER_CCR	\
	(volatile UINT32 *)((SYS_TIMER_BASE) + 0x00)	/* Channel Ctrl (W/O) */
#define SYS_TIMER_CMR	\
	(volatile UINT32 *)((SYS_TIMER_BASE) + 0x04)	/* Channel Mode (R/W) */
#define SYS_TIMER_CVR	\
	(volatile UINT32 *)((SYS_TIMER_BASE) + 0x10)	/* Counter Value (R/O)*/
#define SYS_TIMER_REG_C \
	(volatile UINT32 *)((SYS_TIMER_BASE) + 0x1C)	/* Register C (R/W) */
#define SYS_TIMER_STATUS \
	(volatile UINT32 *)((SYS_TIMER_BASE) + 0x20)	/* Channel Status(R/O)*/
#define SYS_TIMER_IER	\
	(volatile UINT32 *)((SYS_TIMER_BASE) + 0x24)	/* Int Enable (W/O) */
#define SYS_TIMER_IDR	\
	(volatile UINT32 *)((SYS_TIMER_BASE) + 0x28)	/* Int Disable (W/O) */
#define SYS_TIMER_IMR	\
	(volatile UINT32 *)((SYS_TIMER_BASE) + 0x2C)	/* Int Mask (R/W) */

#define AUX_TIMER_CCR	\
	(volatile UINT32 *)((AUX_TIMER_BASE) + 0x00)	/* Channel Ctrl (W/O) */
#define AUX_TIMER_CMR	\
	(volatile UINT32 *)((AUX_TIMER_BASE) + 0x04)	/* Channel Mode (R/W) */
#define AUX_TIMER_CVR	\
	(volatile UINT32 *)((AUX_TIMER_BASE) + 0x10)	/* Counter Value (R/O)*/
#define AUX_TIMER_REG_C \
	(volatile UINT32 *)((AUX_TIMER_BASE) + 0x1C)	/* Register C (R/W) */
#define AUX_TIMER_STATUS \
	(volatile UINT32 *)((AUX_TIMER_BASE) + 0x20)	/* Channel Status(R/O)*/
#define AUX_TIMER_IER	\
	(volatile UINT32 *)((AUX_TIMER_BASE) + 0x24)	/* Int Enable (W/O) */
#define AUX_TIMER_IDR	\
	(volatile UINT32 *)((AUX_TIMER_BASE) + 0x28)	/* Int Disable (W/O) */
#define AUX_TIMER_IMR	\
	(volatile UINT32 *)((AUX_TIMER_BASE) + 0x2C)	/* Int Mask (R/W) */

#define AT91_TIMER_BMR \
	(volatile UINT32 *)((AT91_TIMER_BASE) + 0xC4)	/* Block Mode (R/W) */

#ifdef __cplusplus
}
#endif

#endif	/* __INCat91Timerh */