📄 at91rm9200.h
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#define MC_RCR 0x00 /* MC Remap Control Register */
#define MC_ASR 0x04 /* MC Abort Status Register */
#define MC_AASR 0x08 /* MC Abort Address Status Register */
#define MC_MPR 0x0C /* MC Protection Unit Area */
/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
#define MC_RCB BIT0 /* (MC) Remap Command Bit */
/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
#define MC_UNDADD ((unsigned int) 0x1 << 0) /* (MC) Undefined Addess Abort Status */
#define MC_MISADD ((unsigned int) 0x1 << 1) /* (MC) Misaligned Addess Abort Status */
#define MC_MPU ((unsigned int) 0x1 << 2) /* (MC) Memory protection Unit Abort Status */
#define MC_ABTSZ ((unsigned int) 0x3 << 8) /* (MC) Abort Size Status */
#define MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) /* (MC) Byte */
#define MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) /* (MC) Half-word */
#define MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) /* (MC) Word */
#define MC_ABTTYP ((unsigned int) 0x3 << 10) /* (MC) Abort Type Status */
#define MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) /* (MC) Data Read */
#define MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) /* (MC) Data Write */
#define MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) /* (MC) Code Fetch */
#define MC_MST0 ((unsigned int) 0x1 << 16) /* (MC) Master 0 Abort Source */
#define MC_MST1 ((unsigned int) 0x1 << 17) /* (MC) Master 1 Abort Source */
#define MC_SVMST0 ((unsigned int) 0x1 << 24) /* (MC) Saved Master 0 Abort Source */
#define MC_SVMST1 ((unsigned int) 0x1 << 25) /* (MC) Saved Master 1 Abort Source */
/* -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- */
#define MC_PROT ((unsigned int) 0x3 << 0) /* (MC) Protection */
#define MC_PROT_PNAUNA ((unsigned int) 0x0) /* (MC) Privilege: No Access, User: No Access */
#define MC_PROT_PRWUNA ((unsigned int) 0x1) /* (MC) Privilege: Read/Write, User: No Access */
#define MC_PROT_PRWURO ((unsigned int) 0x2) /* (MC) Privilege: Read/Write, User: Read Only */
#define MC_PROT_PRWURW ((unsigned int) 0x3) /* (MC) Privilege: Read/Write, User: Read/Write */
#define MC_SIZE ((unsigned int) 0xF << 4) /* (MC) Internal Area Size */
#define MC_SIZE_1KB ((unsigned int) 0x0 << 4) /* (MC) Area size 1KByte */
#define MC_SIZE_2KB ((unsigned int) 0x1 << 4) /* (MC) Area size 2KByte */
#define MC_SIZE_4KB ((unsigned int) 0x2 << 4) /* (MC) Area size 4KByte */
#define MC_SIZE_8KB ((unsigned int) 0x3 << 4) /* (MC) Area size 8KByte */
#define MC_SIZE_16KB ((unsigned int) 0x4 << 4) /* (MC) Area size 16KByte */
#define MC_SIZE_32KB ((unsigned int) 0x5 << 4) /* (MC) Area size 32KByte */
#define MC_SIZE_64KB ((unsigned int) 0x6 << 4) /* (MC) Area size 64KByte */
#define MC_SIZE_128KB ((unsigned int) 0x7 << 4) /* (MC) Area size 128KByte */
#define MC_SIZE_256KB ((unsigned int) 0x8 << 4) /* (MC) Area size 256KByte */
#define MC_SIZE_512KB ((unsigned int) 0x9 << 4) /* (MC) Area size 512KByte */
#define MC_SIZE_1MB ((unsigned int) 0xA << 4) /* (MC) Area size 1MByte */
#define MC_SIZE_2MB ((unsigned int) 0xB << 4) /* (MC) Area size 2MByte */
#define MC_SIZE_4MB ((unsigned int) 0xC << 4) /* (MC) Area size 4MByte */
#define MC_SIZE_8MB ((unsigned int) 0xD << 4) /* (MC) Area size 8MByte */
#define MC_SIZE_16MB ((unsigned int) 0xE << 4) /* (MC) Area size 16MByte */
#define MC_SIZE_64MB ((unsigned int) 0xF << 4) /* (MC) Area size 64MByte */
#define MC_BA ((unsigned int) 0x3FFFF << 10) /* (MC) Internal Area Base Address */
/* -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- */
/* -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- */
#define MC_PUEB ((unsigned int) 0x1 << 0) /* (MC) Protection Unit enable Bit */
/* *****************************************************************************
* Static Memory Interface Unit
* *****************************************************************************/
#define SMC_BASE AT91C_BASE_SMC
#define SMC_REG(x) *(volatile UINT32 *)(SMC_BASE + (x))
/* registers offset */
#define SMC_CSR0 0x00 /* Chip Select Register 0 */
#define SMC_CSR1 0x04 /* Chip Select Register 1 */
#define SMC_CSR2 0x08 /* Chip Select Register 2 */
#define SMC_CSR3 0x0C /* Chip Select Register 3 */
#define SMC_CSR4 0x10 /* Chip Select Register 4 */
#define SMC_CSR5 0x14 /* Chip Select Register 5 */
#define SMC_CSR6 0x18 /* Chip Select Register 6 */
#define SMC_CSR7 0x1C /* Chip Select Register 7 */
/* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- */
#define SMC2_NWS ((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */
#define SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */
#define SMC2_TDF ((unsigned int) 0xF << 8) /* (SMC2) Data Float Time */
#define SMC2_BAT ((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */
#define SMC2_DBW ((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */
#define SMC2_DBW_16 ((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */
#define SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
#define SMC2_DRP ((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */
#define SMC2_ACSS ((unsigned int) 0x3 << 16) /* (SMC2) Address to Chip Select Setup */
#define SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end.*/
#define SMC2_ACSS_1_CYCLE ((unsigned int) 0x1 << 16) /* (SMC2) One cycle less at the beginning and the end of the access. */
#define SMC2_ACSS_2_CYCLES ((unsigned int) 0x2 << 16) /* (SMC2) Two cycles less at the beginning and the end of the access. */
#define SMC2_ACSS_3_CYCLES ((unsigned int) 0x3 << 16) /* (SMC2) Three cycles less at the beginning and the end of the access. */
#define SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */
#define SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */
/* *****************************************************************************
* Ethernet MAC (EMAC)
* *****************************************************************************/
#define EMAC_BASE AT91C_BASE_EMAC
#define EMAC_REG(x) *(volatile UINT32 *)(EMAC_BASE + (x))
/* Register Offsets */
#define EMAC_CTL 0x00 /* Network Control Register */
#define EMAC_CFG 0x04 /* Network Configuration Register */
#define EMAC_SR 0x08 /* Network Status Register */
#define EMAC_TAR 0x0C /* Transmit Address Register */
#define EMAC_TCR 0x10 /* Transmit Control Register */
#define EMAC_TSR 0x14 /* Transmit Status Register */
#define EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */
#define EMAC_RSR 0x20 /* Receive Status Register */
#define EMAC_ISR 0x24 /* Interrupt Status Register */
#define EMAC_IER 0x28 /* Interrupt Enable Register */
#define EMAC_IDR 0x2C /* Interrupt Disable Register */
#define EMAC_IMR 0x30 /* Interrupt Mask Register */
#define EMAC_MAN 0x34 /* PHY Maintenance Register */
#define EMAC_FRA 0x40 /* Frames Transmitted OK Register */
#define EMAC_SCOL 0x44 /* Single Collision Frame Register */
#define EMAC_MCOL 0x48 /* Multiple Collision Frame Register */
#define EMAC_OK 0x4C /* Frames Received OK Register */
#define EMAC_SEQE 0x50 /* Frame Check Sequence Error Register */
#define EMAC_ALE 0x54 /* Alignment Error Register */
#define EMAC_DTE 0x58 /* Deferred Transmission Frame Register */
#define EMAC_LCOL 0x5C /* Late Collision Register */
#define EMAC_ECOL 0x60 /* Excessive Collision Register */
#define EMAC_CSE 0x64 /* Carrier Sense Error Register */
#define EMAC_TUE 0x68 /* Transmit Underrun Error Register */
#define EMAC_CDE 0x6C /* Code Error Register */
#define EMAC_ELR 0x70 /* Excessive Length Error Register */
#define EMAC_RJB 0x74 /* Receive Jabber Register */
#define EMAC_USF 0x78 /* Undersize Frame Register */
#define EMAC_SQEE 0x7C /* SQE Test Error Register */
#define EMAC_DRFC 0x80 /* Discarded RX Frame Register */
#define EMAC_HSH 0x90 /* Hash Address High[63:32] */
#define EMAC_HSL 0x94 /* Hash Address Low[31:0] */
#define EMAC_SA1L 0x98 /* Specific Address 1 Low, First 4 bytes */
#define EMAC_SA1H 0x9C /* Specific Address 1 High, Last 2 bytes */
#define EMAC_SA2L 0xA0 /* Specific Address 2 Low, First 4 bytes */
#define EMAC_SA2H 0xA4 /* Specific Address 2 High, Last 2 bytes */
#define EMAC_SA3L 0xA8 /* Specific Address 3 Low, First 4 bytes */
#define EMAC_SA3H 0xAC /* Specific Address 3 High, Last 2 bytes */
#define EMAC_SA4L 0xB0 /* Specific Address 4 Low, First 4 bytes */
#define EMAC_SA4H 0xB4 /* Specific Address 4 High, Last 2 bytes */
/* *****************************************************************************
* SDRAM Memory Interface Unit
* *****************************************************************************/
#define SDRAMC_BASE AT91C_BASE_SDRAMC
#define SDRAMC_REG(x) *(volatile UINT32 *)(SDRAMC_BASE + (x))
/* Registers */
#define SDRAMC_MR 0x00 /* Mode Register */
#define SDRAMC_TR 0x04 /* Refresh Timer Register */
#define SDRAMC_CR 0x08 /* Configuration Register */
#define SDRAMC_SRR 0x0C /* Self Refresh Register */
#define SDRAMC_LPR 0x10 /* Low Power Register */
#define SDRAMC_IER 0x14 /* Interrupt Enable Register */
#define SDRAMC_IDR 0x18 /* Interrupt Disable Register */
#define SDRAMC_IMR 0x1C /* Interrupt Mask Register */
#define SDRAMC_ISR 0x20 /* Interrupt Status Register */
/* Bit Defines */
/* SDRC_MR - Mode Register */
#define SDRAMC_MR_DBW_16 BIT4 /* 1 = SDRAM is 16-bits wide, 0 = 32-bits */
#define SDRAMC_MR_NORM 0x00 /* Normal Mode - All accesses to SDRAM are decoded normally */
#define SDRAMC_MR_NOP 0x01 /* NOP Command is sent to SDRAM */
#define SDRAMC_MR_PRE 0x02 /* Precharge All Command is sent to SDRAM */
#define SDRAMC_MR_MRS 0x03 /* Mode Register Set Command is sent to SDRAM */
#define SDRAMC_MR_REF 0x04 /* Refresh Command is sent to SDRAM */
/* *****************************************************************************
* External Bus Interface Unit
* *****************************************************************************/
#define EBI_CSA 0x00 /* Chip Select Assignment Register */
#define EBI_CFGR 0x04 /* Configuration Register */
/* Bit Defines */
/* EBI_CSA - Chip Select Assignment Register */
#define EBI_CSA_CS4_CF BIT4 /* 1 = CS4-6 are assigned to Compact Flash, 0 = Chip Selects */
#define EBI_CSA_CS3_SMM BIT3 /* 1 = CS3 is assigned to SmartMedia, 0 = Chip Select */
#define EBI_CSA_CS1_SDRAM BIT1 /* 1 = CS1 is assigned to SDRAM, 0 = Chip Select */
#define EBI_CSA_CS0_BF BIT0 /* 1 = CS0 is assigned to Burst Flash, 0 = Chip Select */
/* EBI_CFGR - Configuration Register */
#define EBI_CFGR_DBPU BIT0 /* 1 = Disable D0-15 pullups */
/* *****************************************************************************
* PERIPHERAL ID DEFINITIONS FOR AT91RM9200
* *****************************************************************************/
#define AT91C_ID_FIQ ((unsigned int) 0) /* Advanced Interrupt Controller (FIQ) */
#define AT91C_ID_SYS ((unsigned int) 1) /* System Peripheral */
#define AT91C_ID_PIOA ((unsigned int) 2) /* Parallel IO Controller A */
#define AT91C_ID_PIOB ((unsigned int) 3) /* Parallel IO Controller B */
#define AT91C_ID_PIOC ((unsigned int) 4) /* Parallel IO Controller C */
#define AT91C_ID_PIOD ((unsigned int) 5) /* Parallel IO Controller D */
#define AT91C_ID_US0 ((unsigned int) 6) /* USART 0 */
#define AT91C_ID_US1 ((unsigned int) 7) /* USART 1 */
#define AT91C_ID_US2 ((unsigned int) 8) /* USART 2 */
#define AT91C_ID_US3 ((unsigned int) 9) /* USART 3 */
#define AT91C_ID_MCI ((unsigned int) 10) /* Multimedia Card Interface */
#define AT91C_ID_UDP ((unsigned int) 11) /* USB Device Port */
#define AT91C_ID_TWI ((unsigned int) 12) /* Two-Wire Interface */
#define AT91C_ID_SPI ((unsigned int) 13) /* Serial Peripheral Interface */
#define AT91C_ID_SSC0 ((unsigned int) 14) /* Serial Synchronous Controller 0 */
#define AT91C_ID_SSC1 ((unsigned int) 15) /* Serial Synchronous Controller 1 */
#define AT91C_ID_SSC2 ((unsigned int) 16) /* Serial Synchronous Controller 2 */
#define AT91C_ID_TC0 ((unsigned int) 17) /* Timer Counter 0 */
#define AT91C_ID_TC1 ((unsigned int) 18) /* Timer Counter 1 */
#define AT91C_ID_TC2 ((unsigned int) 19) /* Timer Counter 2 */
#define AT91C_ID_TC3 ((unsigned int) 20) /* Timer Counter 3 */
#define AT91C_ID_TC4 ((unsigned int) 21) /* Timer Counter 4 */
#define AT91C_ID_TC5 ((unsigned int) 22) /* Timer Counter 5 */
#define AT91C_ID_UHP ((unsigned int) 23) /* USB Host port */
#define AT91C_ID_EMAC ((unsigned int) 24) /* Ethernet MAC */
#define AT91C_ID_IRQ0 ((unsigned int) 25) /* Advanced Interrupt Controller (IRQ0) */
#define AT91C_ID_IRQ1 ((unsigned int) 26) /* Advanced Interrupt Controller (IRQ1) */
#define AT91C_ID_IRQ2 ((unsigned int) 27) /* Advanced Interrupt Controller (IRQ2) */
#define AT91C_ID_IRQ3 ((unsigned int) 28) /* Advanced Interrupt Controller (IRQ3) */
#define AT91C_ID_IRQ4 ((unsigned int) 29) /* Advanced Interrupt Controller (IRQ4) */
#define AT91C_ID_IRQ5 ((unsigned int) 30) /* Advanced Interrupt Controller (IRQ5) */
#define AT91C_ID_IRQ6 ((unsigned int) 31) /* Advanced Interrupt Controller (IRQ6) */
#endif /* __INCat91rm9200h */
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