at91rm9200.h

VxWorks BSP for AT91RM92

#define PMC_PCK1        BIT9  /* (PMC) Programmable Clock Output                                  */
#define PMC_PCK2        BIT10 /* (PMC) Programmable Clock Output                                  */
#define PMC_PCK3        BIT11 /* (PMC) Programmable Clock Output                                  */
#define PMC_PCK4        BIT12 /* (PMC) Programmable Clock Output                                  */
#define PMC_PCK5        BIT13 /* (PMC) Programmable Clock Output                                  */
#define PMC_PCK6        BIT14 /* (PMC) Programmable Clock Output                                  */
#define PMC_PCK7        BIT15 /* (PMC) Programmable Clock Output                                  */

/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */

/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */

/* -------- PMC_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
#define PMC_MOR_MOSCEN	  BIT0  /* (PMC) Main oscillator Enable */

/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
#define PMC_CSS           ((unsigned int) 0x3 <<  0) /* (PMC) Programmable Clock Selection             */
#define PMC_CSS_SLOW_CLK  ((unsigned int) 0x0) /* (PMC) Slow Clock is selected                         */
#define PMC_CSS_MAIN_CLK  ((unsigned int) 0x1) /* (PMC) Main Clock is selected                         */
#define PMC_CSS_PLLA_CLK  ((unsigned int) 0x2) /* (PMC) Clock from PLL A is selected                   */
#define PMC_CSS_PLLB_CLK  ((unsigned int) 0x3) /* (PMC) Clock from PLL B is selected                   */
#define PMC_PRES          ((unsigned int) 0x7 <<  2) /* (PMC) Programmable Clock Prescaler             */
#define PMC_PRES_CLK      ((unsigned int) 0x0 <<  2) /* (PMC) Selected clock                           */
#define PMC_PRES_CLK_2    ((unsigned int) 0x1 <<  2) /* (PMC) Selected clock divided by 2              */
#define PMC_PRES_CLK_4    ((unsigned int) 0x2 <<  2) /* (PMC) Selected clock divided by 4              */
#define PMC_PRES_CLK_8    ((unsigned int) 0x3 <<  2) /* (PMC) Selected clock divided by 8              */
#define PMC_PRES_CLK_16   ((unsigned int) 0x4 <<  2) /* (PMC) Selected clock divided by 16             */
#define PMC_PRES_CLK_32   ((unsigned int) 0x5 <<  2) /* (PMC) Selected clock divided by 32             */
#define PMC_PRES_CLK_64   ((unsigned int) 0x6 <<  2) /* (PMC) Selected clock divided by 64             */
#define PMC_MDIV          ((unsigned int) 0x3 <<  8) /* (PMC) Master Clock Division                    */
#define PMC_MDIV_1        ((unsigned int) 0x0 <<  8) /* (PMC) The master clock and the processor clock are the same           */
#define PMC_MDIV_2        ((unsigned int) 0x1 <<  8) /* (PMC) The processor clock is twice as fast as the master clock        */
#define PMC_MDIV_3        ((unsigned int) 0x2 <<  8) /* (PMC) The processor clock is three times faster than the master clock */
#define PMC_MDIV_4        ((unsigned int) 0x3 <<  8) /* (PMC) The processor clock is four times faster than the master clock  */

#define PMC_MCKR_PRES_MASK		0x0000001C				/* for masking out the PRES field */
#define PMC_MCKR_CSS_MASK		0x00000003				/* for masking out the CSS field  */

/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
#define PMC_PCKR_PRES_1			0x00				/* Peripheral Clock = CSS/1                     */ 
#define PMC_PCKR_PRES_2			0x04				/* Peripheral Clock = CSS/2                     */ 
#define PMC_PCKR_PRES_4			0x08				/* Peripheral Clock = CSS/4                     */ 
#define PMC_PCKR_PRES_8			0x1C				/* Peripheral Clock = CSS/8                     */ 
#define PMC_PCKR_PRES_16		0x10				/* Peripheral Clock = CSS/16                    */ 
#define PMC_PCKR_PRES_32		0x14				/* Peripheral Clock = CSS/32                    */ 
#define PMC_PCKR_PRES_64		0x18				/* Peripheral Clock = CSS/64                    */ 
#define PMC_PCKR_CSS_SLOW		0x00				/* Peripheral Clock Source = Slow Clock         */ 
#define PMC_PCKR_CSS_MAIN		0x01				/* Peripheral Clock Source = Main Oscillator    */ 
#define PMC_PCKR_CSS_PLLA		0x02  				/* Peripheral Clock Source = PLL A              */ 
#define PMC_PCKR_CSS_PLLB		0x03				/* Peripheral Clock Source = PLL B              */ 
                                                                                                         
/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
#define PMC_MOSCS       ((unsigned int) 0x1 <<  0) /* (PMC) MOSC Status/Enable/Disable/Mask     */
#define PMC_LOCKA       ((unsigned int) 0x1 <<  1) /* (PMC) PLL A Status/Enable/Disable/Mask    */
#define PMC_LOCKB       ((unsigned int) 0x1 <<  2) /* (PMC) PLL B Status/Enable/Disable/Mask    */
#define PMC_MCKRDY      ((unsigned int) 0x1 <<  3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask  */
#define PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
#define PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
#define PMC_PCK2RDY     ((unsigned int) 0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
#define PMC_PCK3RDY     ((unsigned int) 0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
#define PMC_PCK4RDY     ((unsigned int) 0x1 << 12) /* (PMC) PCK4_RDY Status/Enable/Disable/Mask */
#define PMC_PCK5RDY     ((unsigned int) 0x1 << 13) /* (PMC) PCK5_RDY Status/Enable/Disable/Mask */
#define PMC_PCK6RDY     ((unsigned int) 0x1 << 14) /* (PMC) PCK6_RDY Status/Enable/Disable/Mask */
#define PMC_PCK7RDY     ((unsigned int) 0x1 << 15) /* (PMC) PCK7_RDY Status/Enable/Disable/Mask */

/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */

/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */

/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */
                                                                   
#define PMC_INT_PCK7_RDY		BIT15
#define PMC_INT_PCK6_RDY		BIT14
#define PMC_INT_PCK5_RDY		BIT13
#define PMC_INT_PCK4_RDY		BIT12
#define PMC_INT_PCK3_RDY		BIT11
#define PMC_INT_PCK2_RDY		BIT10
#define PMC_INT_PCK1_RDY		BIT9
#define PMC_INT_PCK0_RDY		BIT8
#define PMC_INT_MCK_RDY			BIT3
#define PMC_INT_LOCKB			BIT2
#define PMC_INT_LCKA			BIT1
#define PMC_INT_MOSCS			BIT0


/* *****************************************************************************
 * System timer (ST)
 * *****************************************************************************/
#define ST_BASE		0xFFFFFD00
#define ST_REG(x)	*(volatile UINT32 *)(ST_BASE + (x))

/* Register Offsets */
#define ST_CR 		0x00    /* Control Register                            */
#define ST_PIMR 	0x04    /* Period Interval Mode Register               */ 
#define ST_WDMR 	0x08    /* Watchdog Mode Register                      */ 
#define ST_RTMR 	0x0C    /* Real-time Mode Register                     */ 
#define ST_SR 		0x10    /* Status Register                             */ 
#define ST_IER 		0x14    /* Interrupt Enable Register                   */ 
#define ST_IDR 		0x18    /* Interrupt Disable Register                  */ 
#define ST_IMR 		0x1C    /* Interrupt Mask Register                     */ 
#define ST_RTAR 	0x20    /* Real-time Alarm Register                    */ 
#define ST_CRTR 	0x24    /* Current Real-time Register                  */ 
        
/* -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- */
#define ST_WDRST        ((unsigned int) 0x1 <<  0)    /* (ST) Watchdog Timer Restart */

/* -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- */ 
#define ST_PIV          ((unsigned int) 0xFFFF <<  0) /* (ST) Watchdog Timer Restart */

/* -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- */
#define ST_WDV          ((unsigned int) 0xFFFF <<  0) /* (ST) Watchdog Timer Restart */
#define ST_RSTEN        ((unsigned int) 0x1 << 16)    /* (ST) Reset Enable */
#define ST_EXTEN        ((unsigned int) 0x1 << 17)    /* (ST) External Signal Assertion Enable */

/* -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- */
#define ST_RTPRES       ((unsigned int) 0xFFFF <<  0) /* (ST) Real-time Timer Prescaler Value */

/* -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- */
#define ST_PITS         ((unsigned int) 0x1 <<  0)    /* (ST) Period Interval Timer Interrupt */
#define ST_WDOVF        ((unsigned int) 0x1 <<  1)    /* (ST) Watchdog Overflow               */
#define ST_RTTINC       ((unsigned int) 0x1 <<  2)    /* (ST) Real-time Timer Increment       */
#define ST_ALMS         ((unsigned int) 0x1 <<  3)    /* (ST) Alarm Status                    */

/* -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- */

/* -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- */

/* -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- */

/* -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- */
#define ST_ALMV         ((unsigned int) 0xFFFFF <<  0) /* (ST) Alarm Value Value */

/* -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- */
#define ST_CRTV         ((unsigned int) 0xFFFFF <<  0) /* (ST) Current Real-time Value */

                                                                    
/* *****************************************************************************
 * Real Time Clock (RTC)
 * *****************************************************************************/
#define RTC_BASE	0xFFFFFE00
#define RTC_REG(x)	*(volatile UINT32 *)(RTC_BASE + (x))

/* Register Offsets */
#define RTC_CR 		0x00    /* Control Register                            */ 
#define RTC_MR 		0x04    /* Mode Register                               */ 
#define RTC_TIMR 	0x08    /* Time Register                               */ 
#define RTC_CALR 	0x0C    /* Calendar Register                           */ 
#define RTC_TIMALR 	0x10    /* Time Alarm Register                         */ 
#define RTC_CALALR 	0x14    /* Calendar Alarm Register                     */ 
#define RTC_SR 		0x18    /* Status Register                             */ 
#define RTC_SCCR 	0x1C    /* Status Clear Command Register               */ 
#define RTC_IER 	0x20    /* Interrupt Enable Register                   */ 
#define RTC_IDR 	0x24    /* Interrupt Disable Register                  */ 
#define RTC_IMR 	0x28    /* Interrupt Mask Register                     */ 
#define RTC_VER 	0x2C    /* Valid Entry Register                        */ 
                                                                    
/* -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- */                                                  
#define RTC_UPDTIM            ((unsigned int) 0x1 <<  0) /* (RTC) Update Request Time Register                           */
#define RTC_UPDCAL            ((unsigned int) 0x1 <<  1) /* (RTC) Update Request Calendar Register                       */
#define RTC_TIMEVSEL          ((unsigned int) 0x3 <<  8) /* (RTC) Time Event Selection                                   */
#define RTC_TIMEVSEL_MINUTE   ((unsigned int) 0x0 <<  8) /* (RTC) Minute change.                                         */
#define RTC_TIMEVSEL_HOUR     ((unsigned int) 0x1 <<  8) /* (RTC) Hour change.                                           */
#define RTC_TIMEVSEL_DAY24    ((unsigned int) 0x2 <<  8) /* (RTC) Every day at midnight.                                 */
#define RTC_TIMEVSEL_DAY12    ((unsigned int) 0x3 <<  8) /* (RTC) Every day at noon.                                     */
#define RTC_CALEVSEL          ((unsigned int) 0x3 << 16) /* (RTC) Calendar Event Selection                               */
#define RTC_CALEVSEL_WEEK     ((unsigned int) 0x0 << 16) /* (RTC) Week change (every Monday at time 00:00:00).           */
#define RTC_CALEVSEL_MONTH    ((unsigned int) 0x1 << 16) /* (RTC) Month change (every 01 of each month at time 00:00:00).*/
#define RTC_CALEVSEL_YEAR     ((unsigned int) 0x2 << 16) /* (RTC) Year change (every January 1 at time 00:00:00).        */

/* -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- */
#define RTC_HRMOD             ((unsigned int) 0x1 <<  0) /* (RTC) 12-24 hour Mode */

/* -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- */
#define RTC_SEC               ((unsigned int) 0x7F <<  0) /* (RTC) Current Second                           */
#define RTC_MIN               ((unsigned int) 0x7F <<  8) /* (RTC) Current Minute                           */
#define RTC_HOUR              ((unsigned int) 0x1F << 16) /* (RTC) Current Hour                             */
#define RTC_AMPM              ((unsigned int) 0x1 << 22)  /* (RTC) Ante Meridiem, Post Meridiem Indicator   */

/* -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- */
#define RTC_CENT              ((unsigned int) 0x3F <<  0) /* (RTC) Current Century */
#define RTC_YEAR              ((unsigned int) 0xFF <<  8) /* (RTC) Current Year    */
#define RTC_MONTH             ((unsigned int) 0x1F << 16) /* (RTC) Current Month   */
#define RTC_DAY               ((unsigned int) 0x7 << 21)  /* (RTC) Current Day     */
#define RTC_DATE              ((unsigned int) 0x3F << 24) /* (RTC) Current Date    */

/* -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- */
#define RTC_SECEN             ((unsigned int) 0x1 <<  7) /* (RTC) Second Alarm Enable */
#define RTC_MINEN             ((unsigned int) 0x1 << 15) /* (RTC) Minute Alarm        */
#define RTC_HOUREN            ((unsigned int) 0x1 << 23) /* (RTC) Current Hour        */

/* -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- */
#define RTC_MONTHEN           ((unsigned int) 0x1 << 23) /* (RTC) Month Alarm Enable     */
#define RTC_DATEEN            ((unsigned int) 0x1 << 31) /* (RTC) Date Alarm Enable      */

/* -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- */
#define RTC_ACKUPD            ((unsigned int) 0x1 <<  0) /* (RTC) Acknowledge for Update */
#define RTC_ALARM             ((unsigned int) 0x1 <<  1) /* (RTC) Alarm Flag             */
#define RTC_SECEV             ((unsigned int) 0x1 <<  2) /* (RTC) Second Event           */
#define RTC_TIMEV             ((unsigned int) 0x1 <<  3) /* (RTC) Time Event             */
#define RTC_CALEV             ((unsigned int) 0x1 <<  4) /* (RTC) Calendar event         */

/* -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- */

/* -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- */

/* -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- */

/* -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- */

/* -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- */
#define RTC_NVTIM       ((unsigned int) 0x1 <<  0) /* (RTC) Non valid Time          */
#define RTC_NVCAL       ((unsigned int) 0x1 <<  1) /* (RTC) Non valid Calendar      */
#define RTC_NVTIMALR    ((unsigned int) 0x1 <<  2) /* (RTC) Non valid time Alarm    */
#define RTC_NVCALALR    ((unsigned int) 0x1 <<  3) /* (RTC) Nonvalid Calendar Alarm */

                                                                    
/* *****************************************************************************
 * Memory Controller (MC)
 * *****************************************************************************/
#define MC_BASE	    0xFFFFFF00
#define MC_REG(x)	*(volatile UINT32 *)(ST_BASE + (x))

/* Register Offsets */