📄 at91rm9200.h
字号:
/* *****************************************************************************
* Universal Synchronous Asynchronous Receiver Transceiver (USART)
* *****************************************************************************/
#define USART0_BASE AT91C_BASE_US0
#define USART0_REG(x) *(volatile UINT32 *)(USART0_BASE + (x))
#define USART1_BASE AT91C_BASE_US1
#define USART1_REG(x) *(volatile UINT32 *)(USART1_BASE + (x))
#define USART2_BASE AT91C_BASE_US2
#define USART2_REG(x) *(volatile UINT32 *)(USART2_BASE + (x))
#define USART3_BASE AT91C_BASE_US3
#define USART3_REG(x) *(volatile UINT32 *)(USART3_BASE + (x))
/* Register Offsets */
#define US_CR 0x00 /* (USART) Receive Holding Register */
#define US_MR 0x04 /* (USART) Mode Register */
#define US_IER 0x08 /* (USART) Interrupt Enable Register */
#define US_IDR 0x0C /* (USART) Interrupt Disable Register */
#define US_IMR 0x10 /* (USART) Interrupt Mask Register */
#define US_CSR 0x14 /* (USART) Channel Status Register */
#define US_RHR 0x18 /* (USART) Receiver Holding Register */
#define US_THR 0x1C /* (USART) Transmitter Holding Register */
#define US_BRGR 0x20 /* (USART) Baud Rate Generator Register */
#define US_RTOR 0x24 /* (USART) Receiver Time-out Register */
#define US_TTGR 0x28 /* (USART) Transmitter Time-guard Register */
#define US_FDI 0x40 /* (USART) FI_DI_Ratio Register */
#define US_NER 0x44 /* (USART) Nb Errors Register */
#define US_IF 0x4C /* (USART) IRDA_FILTER Register */
/* *****************************************************************************
* Serial Synchronous Controller (SSC)
* *****************************************************************************/
#define SSC0_BASE AT91C_BASE_SSC0
#define SSC0_REG(x) *(volatile UINT32 *)(AT91C_BASE_SSC0 + (x))
#define SSC1_BASE AT91C_BASE_SSC1
#define SSC1_REG(x) *(volatile UINT32 *)(AT91C_BASE_SSC1 + (x))
#define SSC2_BASE AT91C_BASE_SSC2
#define SSC2_REG(x) *(volatile UINT32 *)(AT91C_BASE_SSC2 + (x))
/* Register Offsets */
#define SSC_CR 0x00 /* (SSC) Control Register */
#define SSC_CMR 0x04 /* (SSC) Clock Mode Register */
#define SSC_RCMR 0x10 /* (SSC) Receive Clock ModeRegister */
#define SSC_RFMR 0x14 /* (SSC) Receive Frame Mode Register */
#define SSC_TCMR 0x18 /* (SSC) Transmit Clock Mode Register */
#define SSC_TFMR 0x1C /* (SSC) Transmit Frame Mode Register */
#define SSC_RHR 0x20 /* (SSC) Receive Holding Register */
#define SSC_THR 0x24 /* (SSC) Transmit Holding Register */
#define SSC_RSHR 0x30 /* (SSC) Receive Sync Holding Register */
#define SSC_TSHR 0x34 /* (SSC) Transmit Sync Holding Register */
#define SSC_SR 0x40 /* (SSC) Status Register */
#define SSC_IER 0x44 /* (SSC) Interrupt Enable Register */
#define SSC_IDR 0x48 /* (SSC) Interrupt Disable Register */
#define SSC_IMR 0x4C /* (SSC) Interrupt Mask Register */
/* *****************************************************************************
* Timer Counter (TC)
* *****************************************************************************/
#define TC0_BASE AT91C_BASE_TC0
#define TC0_REG(x) *(volatile UINT32 *)(AT91C_BASE_TC0 + (x))
#define TC1_BASE AT91C_BASE_TC1
#define TC1_REG(x) *(volatile UINT32 *)(AT91C_BASE_TC1 + (x))
#define TC2_BASE AT91C_BASE_TC2
#define TC2_REG(x) *(volatile UINT32 *)(AT91C_BASE_TC2 + (x))
#define TC3_BASE AT91C_BASE_TC3
#define TC3_REG(x) *(volatile UINT32 *)(AT91C_BASE_TC3 + (x))
#define TC4_BASE AT91C_BASE_TC4
#define TC4_REG(x) *(volatile UINT32 *)(AT91C_BASE_TC4 + (x))
#define TC5_BASE AT91C_BASE_TC5
#define TC5_REG(x) *(volatile UINT32 *)(AT91C_BASE_TC5 + (x))
/* Register Offsets */
#define TC_BCR 0xC0 /* (TC) Block Control Register */
#define TC_BMR 0xC4 /* (TC) Block Mode Register */
#define TC_CCR 0x00 /* (TC) Channel Control Register */
#define TC_CMR 0x04 /* (TC) Channel Mode Register */
#define TC_CV 0x10 /* (TC) Counter Value */
#define TC_RA 0x14 /* (TC) Register A */
#define TC_RB 0x18 /* (TC) Register B */
#define TC_RC 0x1C /* (TC) Register C */
#define TC_SR 0x20 /* (TC) Status Register */
#define TC_IER 0x24 /* (TC) Interrupt Enable Register */
#define TC_IDR 0x28 /* (TC) Interrupt Disable Register */
#define TC_IMR 0x2C /* (TC) Interrupt Mask Register */
/* *****************************************************************************
* MultiMedia Card Interface (MCI)
* *****************************************************************************/
#define MCI_BASE AT91C_BASE_MCI
#define MCI_REG(x) *(volatile UINT32 *)(AT91C_BASE_MCI + (x))
/* Register Offsets */
#define MCI_CR 0x00 /* (MCI) MCI Control Register */
#define MCI_MR 0x04 /* (MCI) MCI Mode Register */
#define MCI_DTOR 0x08 /* (MCI) MCI Data Timeout Register */
#define MCI_SDCR 0x0C /* (MCI) MCI SD Card Register */
#define MCI_ARGR 0x10 /* (MCI) MCI Argument Register */
#define MCI_CMDR 0x14 /* (MCI) MCI Command Register */
#define MCI_RSPR 0x20 /* (MCI) MCI Response Register */
#define MCI_RDR 0x30 /* (MCI) MCI Receive Data Register */
#define MCI_TDR 0x34 /* (MCI) MCI Transmit Data Register */
#define MCI_SR 0x40 /* (MCI) MCI Status Register */
#define MCI_IER 0x44 /* (MCI) MCI Interrupt Enable Register */
#define MCI_IDR 0x48 /* (MCI) MCI Interrupt Disable Register */
#define MCI_IMR 0x4C /* (MCI) MCI Interrupt Mask Register */
/* *****************************************************************************
* USB Device Port (UDP)
* *****************************************************************************/
#define UDP_BASE AT91C_BASE_UDP
#define UDP_REG(x) *(volatile UINT32 *)(AT91C_BASE_UDP + (x))
/* Register Offsets */
#define UDP_IDR 0x14 /* (UDP) Interrupt Disable Register */
#define UDP_CSR0 0x30 /* (UDP) Endpoint 0 Control and Status Register */
#define UDP_CSR1 0x34 /* (UDP) Endpoint 1 Control and Status Register */
#define UDP_CSR2 0x38 /* (UDP) Endpoint 2 Control and Status Register */
#define UDP_CSR3 0x3C /* (UDP) Endpoint 3 Control and Status Register */
#define UDP_CSR4 0x40 /* (UDP) Endpoint 4 Control and Status Register */
#define UDP_CSR5 0x44 /* (UDP) Endpoint 5 Control and Status Register */
#define UDP_CSR6 0x48 /* (UDP) Endpoint 6 Control and Status Register */
#define UDP_CSR7 0x4C /* (UDP) Endpoint 7 Control and Status Register */
/* *****************************************************************************
* USB Host Port (UHP)
* *****************************************************************************/
#define UHP_BASE AT91C_BASE_UHP
#define UHP_REG(x) *(volatile UINT32 *)(AT91C_BASE_UHP + (x))
/* *****************************************************************************
* Parallel I/O Unit (PIO)
* There are four PIO blocks - A, B, C and D. They all have the
* same register set, but different base addresses
* *****************************************************************************/
/* Port A */
#define PIOA_BASE 0xFFFFF400
#define PIOA_REG(x) *(volatile UINT32 *)(PIOA_BASE + (x))
/* Port B */
#define PIOB_BASE 0xFFFFF600
#define PIOB_REG(x) *(volatile UINT32 *)(PIOB_BASE + (x))
/* Port C */
#define PIOC_BASE 0xFFFFF800
#define PIOC_REG(x) *(volatile UINT32 *)(PIOC_BASE + (x))
/* Port D */
#define PIOD_BASE 0xFFFFFA00
#define PIOD_REG(x) *(volatile UINT32 *)(PIOD_BASE + (x))
/* Registers */
#define PIO_PER 0x00 /* PIO Enable Register */
#define PIO_PDR 0x04 /* PIO Disable Register */
#define PIO_PSR 0x08 /* PIO Status Register */
#define PIO_OER 0x10 /* Output Enable Register */
#define PIO_ODR 0x14 /* Output Disable Registerr */
#define PIO_OSR 0x18 /* Output Status Register */
#define PIO_IFER 0x20 /* Input Filter Enable Register */
#define PIO_IFDR 0x24 /* Input Filter Disable Register */
#define PIO_IFSR 0x28 /* Input Filter Status Register */
#define PIO_SODR 0x30 /* Set Output Data Register */
#define PIO_CODR 0x34 /* Clear Output Data Register */
#define PIO_ODSR 0x38 /* Output Data Status Register */
#define PIO_PDSR 0x3c /* Pin Data Status Register */
#define PIO_IER 0x40 /* Interrupt Enable Register */
#define PIO_IDR 0x44 /* Interrupt Disable Register */
#define PIO_IMR 0x48 /* Interrupt Mask Register */
#define PIO_ISR 0x4c /* Interrupt Status Register */
#define PIO_MDER 0x50 /* Multi-driver Enable Register */
#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
#define PIO_MDSR 0x58 /* Multi-driver Status Register */
#define PIO_PUDR 0x60 /* Pull-up Disable Register */
#define PIO_PUER 0x64 /* Pull-up Enable Register */
#define PIO_PUSR 0x68 /* Pad Pull-up Status Register */
#define PIO_ASR 0x70 /* Select A Register */
#define PIO_BSR 0x74 /* Select B Register */
#define PIO_ABSR 0x78 /* AB Select Status Register */
#define PIO_OWER 0xA0 /* Output Write Enable Register */
#define PIO_OWDR 0xA4 /* Output Write Disable Register */
#define PIO_OWSR 0xA8 /* Output Write Status Register */
/* *****************************************************************************
* Power Management and Clock Control (PMC)
* *****************************************************************************/
#define PMC_BASE 0xFFFFFC00
#define PMC_REG(x) *(volatile UINT32 *)(PMC_BASE + (x))
/* Register Offsets */
#define PMC_SCER 0x00 /* System Clock Enable Register */
#define PMC_SCDR 0x04 /* System Clock Disable Register */
#define PMC_SCSR 0x08 /* System Clock Status Register */
#define PMC_PCER 0x10 /* Peripheral Clock Enable Register */
#define PMC_PCDR 0x14 /* Peripheral Clock Disable Register */
#define PMC_PCSR 0x18 /* Peripheral Clock Status Register */
#define PMC_MOR 0x20 /* Main Oscillator Register */
#define PMC_MCFR 0x24 /* Main Clock Frequency Register */
#define PMC_PLLAR 0x28 /* PLL A Register */
#define PMC_PLLBR 0x2C /* PLL B Register */
#define PMC_MCKR 0x30 /* Master Clock Register */
#define PMC_PCKR0 0x40 /* Programmable Clock Register 0 */
#define PMC_PCKR1 0x44 /* Programmable Clock Register 1 */
#define PMC_PCKR2 0x48 /* Programmable Clock Register 2 */
#define PMC_PCKR3 0x4C /* Programmable Clock Register 3 */
#define PMC_PCKR4 0x50 /* Programmable Clock Register 4 */
#define PMC_PCKR5 0x54 /* Programmable Clock Register 5 */
#define PMC_PCKR6 0x58 /* Programmable Clock Register 6 */
#define PMC_PCKR7 0x5C /* Programmable Clock Register 7 */
#define PMC_IER 0x60 /* Interrupt Enable Register */
#define PMC_IDR 0x64 /* Interrupt Disable Register */
#define PMC_SR 0x68 /* Status Register */
#define PMC_IMR 0x6C /* Interrupt Mask Register */
/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
#define PMC_PCK BIT0 /* (PMC) Processor Clock */
#define PMC_UDP BIT1 /* (PMC) USB Device Port Clock */
#define PMC_MCKUDP BIT2 /* (PMC) USB Device Port Master Clock Automatic Disable on Suspend */
#define PMC_UHP BIT4 /* (PMC) USB Host Port Clock */
#define PMC_PCK0 BIT8 /* (PMC) Programmable Clock Output */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -