📄 at91emacend.h
字号:
/* at91EmacEnd.h - AT91RM9200 Ethernet network interface header */
/* Copyright 1990-2004 Wind River Systems, Inc. */
/*
modification history
--------------------
01a,24sep04pdr written.
*/
#ifndef __INCat91EmacEndh
#define __INCat91EmacEndh
/* includes */
#ifdef __cplusplus
extern "C" {
#endif
#include "at91rm9200.h"
/* defines */
#define EMAC_END_DEV_NAME "emac"
#define EMAC_END_DEV_LEN (sizeof(EMAC_END_DEV_NAME) + 1)
#define EMAC_END_TX_DEF_NUM 32 /* default number of TX buffers and descriptors */
#define EMAC_END_RX_DEF_NUM 32 /* default number of RX buffers and descriptors */
#define EMAC_END_LOAN_NUM 64 /* loaned buffers */
#define EMAC_END_TX_MIN 8 /* min number of TX buffers and descriptors */
#define EMAC_END_RX_MIN 8 /* min number of RX buffers and descriptors */
#define EMAC_END_TX_MAX 128 /* max number of TX buffers and descriptors (limited by the memory available !) */
#define EMAC_END_RX_MAX 1024 /* max number of RX buffers and descriptors (limitation from documentation) */
/* rx/tx buffer descriptors definitions */
#define CL_OVERHEAD 4 /* prepended cluster overhead */
#define CL_ALIGNMENT 4 /* cluster required alignment */
#define MBLK_ALIGNMENT 4 /* mBlks required alignment */
#define EMAC_END_BD_ALIGN 0x40 /* required alignment for RBDs */
#define EMAC_END_MAX_PCK_SZ (ETHERMTU + SIZEOF_ETHERHEADER + ETHER_CRC_LEN)
/* EMAC register definitions */
/* Control Register, EMAC_CTL, Offset 0x0 */
#define EMAC_CTL_LB BIT0 /* 1 = Set Loopback output signal */
#define EMAC_CTL_LBL BIT1 /* 1 = Loopback local. */
#define EMAC_CTL_RE BIT2 /* 1 = Receive enable. */
#define EMAC_CTL_TE BIT3 /* 1 = Transmit enable. */
#define EMAC_CTL_MPE BIT4 /* 1 = Management port enable. */
#define EMAC_CTL_CSR BIT5 /* Write 1 to clear statistics registers. */
#define EMAC_CTL_ISR BIT6 /* Write to increment all statistics registers for test use. */
#define EMAC_CTL_WES BIT7 /* 1 = Enable writing to statistics registers for test use. */
#define EMAC_CTL_BP BIT8 /* 1 = Force collision on all RX frames in HDX mode. */
/* Configuration Register, EMAC_CFG, Offset 0x4 */
#define EMAC_CFG_SPD BIT0 /* 1 = 10/100 Speed (no functional effect) */
#define EMAC_CFG_FD BIT1 /* 1 = Full duplex. */
#define EMAC_CFG_BR BIT2 /* write 0 */
#define EMAC_CFG_CAF BIT4 /* 1 = accept all frames */
#define EMAC_CFG_NBC BIT5 /* 1 = disable reception of broadcast frames */
#define EMAC_CFG_MTI BIT6 /* 1 = Multicast hash enable */
#define EMAC_CFG_UNI BIT7 /* 1 = Unicast hash enable. */
#define EMAC_CFG_BIG BIT8 /* 1 = enable reception of 802.3 1522 byte frames */
#define EMAC_CFG_EAE BIT9 /* write 0 */
#define EMAC_CFG_CLK_8 (0 << 10) /* MII Clock = HCLK divided by 8 */
#define EMAC_CFG_CLK_16 (1 << 10) /* MII Clock = HCLK divided by 16 */
#define EMAC_CFG_CLK_32 (2 << 10) /* MII Clock = HCLK divided by 32 */
#define EMAC_CFG_CLK_64 (3 << 10) /* MII Clock = HCLK divided by 64 */
#define EMAC_CFG_RTY BIT12 /* Retry Test Mode - Must be 0 */
#define EMAC_CFG_RMII BIT13 /* Reduced MII Mode Enable */
/* Status Register, EMAC_SR, Offset 0x8 */
#define EMAC_LINK BIT0 /* Link pin (real time value or chang indication?) */
#define EMAC_MDIO BIT1 /* Real Time state of MDIO pin */
#define EMAC_IDLE BIT2 /* 0 = PHY Logic is idle, 1 = PHY Logic is running */
/* Transmit Control Register, EMAC_TCR, Offset 0x10 */
#define EMAC_TCR_LEN(_x_) ((_x_ & 0x7FF) << 0) /* Transmit frame length minus CRC length (if any) */
#define EMAC_TCR_NCRC BIT15 /* Do not append CRC on Transmit */
/* Transmit Status Register, EMAC_TSR, Offset 0x14 */
#define EMAC_TSR_OVR BIT0 /* 1 = Transmit buffer overrun */
#define EMAC_TSR_COL BIT1 /* 1 = Collision occured */
#define EMAC_TSR_RLE BIT2 /* 1 = Retry lmimt exceeded */
#define EMAC_TSR_TXIDLE BIT3 /* 1 = Transmitter is idle */
#define EMAC_TSR_BNQ BIT4 /* 1 = Transmit buffer not queued */
#define EMAC_TSR_COMP BIT5 /* 1 = Transmit complete */
#define EMAC_TSR_UND BIT6 /* 1 = Transmit underrun */
/* Receive Status Register, EMAC_RSR, Offset 0x20 */
#define EMAC_RSR_BNA BIT0 /* 1 = Buffer not available */
#define EMAC_RSR_REC BIT1 /* 1 = Frame received */
#define EMAC_RSR_OVR BIT2 /* 1 = Receive overrun */
/* Interrupt Status Register, EMAC_ISR, Offsen 0x24 */
/* Interrupt Enable Register, EMAC_IER, Offset 0x28 */
/* Interrupt Disable Register, EMAC_IDR, Offset 0x2c */
/* Interrupt Mask Register, EMAC_IMR, Offset 0x30 */
#define EMAC_INT_DONE BIT0 /* Phy management done */
#define EMAC_INT_RCOM BIT1 /* Receive complete */
#define EMAC_INT_RBNA BIT2 /* Receive buffer not available */
#define EMAC_INT_TOVR BIT3 /* Transmit buffer overrun */
#define EMAC_INT_TUND BIT4 /* Transmit buffer underrun */
#define EMAC_INT_RTRY BIT5 /* Transmit Retry limt */
#define EMAC_INT_TBRE BIT6 /* Transmit buffer register empty */
#define EMAC_INT_TCOM BIT7 /* Transmit complete */
#define EMAC_INT_TIDLE BIT9 /* Transmit idle */
#define EMAC_INT_ROVR BIT10 /* Receive overrun */
#define EMAC_INT_ABT BIT11 /* Abort on DMA transfer */
/* PHY Maintenance Register, EMAC_MAN, Offset 0x34 */
#define EMAC_MAN_DATA(_x_) ((_x_ & 0xFFFF) << 0) /* PHY data register */
#define EMAC_MAN_CODE (0x3 << 6) /* IEEE Code */
#define EMAC_MAN_REGA(_x_) ((_x_ & 0x1F) << 18) /* PHY register address */
#define EMAC_MAN_PHYA(_x_) ((_x_ & 0x1F) << 23) /* PHY address */
#define EMAC_MAN_WRITE (0x1 << 28) /* Transfer is a write */
#define EMAC_MAN_READ (0x2 << 28) /* Transfer is a read */
#define EMAC_MAN_HIGH BIT30 /* Must be set */
/* MII definitions */
#define ETHER_CRC_LEN 0x4 /* CRC length in bytes */
#define MII_MAX_PHY_NUM 0x20 /* max number of attached PHYs */
#define MII_CTRL_REG 0x0 /* Control Register */
#define MII_STAT_REG 0x1 /* Status Register */
#define MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */
#define MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */
#define MII_AN_ADS_REG 0x4 /* Auto-Negotiation */
/* Advertisement Register */
#define MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */
/* partner ability Register */
#define MII_AN_EXP_REG 0x6 /* Auto-Negotiation */
/* Expansion Register */
#define MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */
/* next-page transmit Register */
/* MII control register bit */
#define MII_CR_COLL_TEST 0x0080 /* collision test */
#define MII_CR_FDX 0x0100 /* FDX =1, half duplex =0 */
#define MII_CR_RESTART 0x0200 /* restart auto negotiation */
#define MII_CR_ISOLATE 0x0400 /* isolate PHY from MII */
#define MII_CR_POWER_DOWN 0x0800 /* power down */
#define MII_CR_AUTO_EN 0x1000 /* auto-negotiation enable */
#define MII_CR_100 0x2000 /* 0 = 10mb, 1 = 100mb */
#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
#define MII_CR_NORM_EN 0x0000 /* just enable the PHY */
/* MII Status register bit definitions */
#define MII_SR_LINK_STATUS 0x0004 /* link Status -- 1 = link */
#define MII_SR_AUTO_SEL 0x0008 /* auto speed select capable */
#define MII_SR_REMOTE_FAULT 0x0010 /* Remote fault detect */
#define MII_SR_AUTO_NEG 0x0020 /* auto negotiation complete */
#define MII_SR_10T_HALF_DPX 0x0800 /* 10BaseT HD capable */
#define MII_SR_10T_FULL_DPX 0x1000 /* 10BaseT FD capable */
#define MII_SR_TX_HALF_DPX 0x2000 /* TX HD capable */
#define MII_SR_TX_FULL_DPX 0x4000 /* TX FD capable */
#define MII_SR_T4 0x8000 /* T4 capable */
/* MII Link Code word bit definitions */
#define MII_BP_FAULT 0x2000 /* remote fault */
#define MII_BP_ACK 0x4000 /* acknowledge */
#define MII_BP_NP 0x8000 /* nexp page is supported */
/* MII Next Page bit definitions */
#define MII_NP_TOGGLE 0x0800 /* toggle bit */
#define MII_NP_ACK2 0x1000 /* acknowledge two */
#define MII_NP_MSG 0x2000 /* message page */
#define MII_NP_ACK1 0x4000 /* acknowledge one */
#define MII_NP_NP 0x8000 /* nexp page will follow */
/* MII Expansion Register bit definitions */
#define MII_EXP_FAULT 0x0010 /* parallel detection fault */
#define MII_EXP_PRTN_NP 0x0008 /* link partner next-page able */
#define MII_EXP_LOC_NP 0x0004 /* local PHY next-page able */
#define MII_EXP_PR 0x0002 /* full page received */
#define MII_EXP_PRT_AN 0x0001 /* link partner auto negotiation able */
/* technology ability field bit definitions */
#define MII_TECH_10BASE_T 0x0020 /* 10Base-T */
#define MII_TECH_10BASE_FD 0x0040 /* 10Base-T Full Duplex */
#define MII_TECH_100BASE_TX 0x0080 /* 100Base-TX */
#define MII_TECH_100BASE_TX_FD 0x0100 /* 100Base-TX Full Duplex */
#define MII_TECH_100BASE_T4 0x0200 /* 100Base-T4 */
#define MII_TECH_MASK 0x1fe0 /* technology abilities mask */
#define MII_AN_FAIL 0x10 /* auto-negotiation fail */
#define MII_STAT_FAIL 0x20 /* errors in the status register */
#define FEC_END_PHY_NO_ABLE 0x40 /* the PHY lacks some abilities */
/* Bit assignments for Receive Buffer Descriptor */
/* Address - Word 0 */
#define RXBUF_ADD_BASE_MASK 0xfffffffc /* Base address of the receive buffer in memory */
#define RXBUF_ADD_WRAP BIT1 /* If this bit is set, this is the last buffer in the ring */
#define RXBUF_ADD_OWNED BIT0 /* 1 = SW owns the pointer, 0 = MAC owns buffer */
/* Status - Word 1 */
#define RXBUF_STAT_BCAST BIT31 /* Global all ones broadcast address detected */
#define RXBUF_STAT_MULTI BIT30 /* Multicast hash match */
#define RXBUF_STAT_UNI BIT29 /* Unicast hash match */
#define RXBUF_STAT_EXT BIT28 /* External address (optional) */
#define RXBUF_STAT_UNK BIT27 /* Unknown source address (reserved for future use) */
#define RXBUF_STAT_LOC1 BIT26 /* Local address match (Specific address 1 match) */
#define RXBUF_STAT_LOC2 BIT25 /* Local address match (Specific address 2 match) */
#define RXBUF_STAT_LOC3 BIT24 /* Local address match (Specific address 3 match) */
#define RXBUF_STAT_LOC4 BIT23 /* Local address match (Specific address 4 match) */
#define RXBUF_STAT_LEN_MASK 0x7ff /* Length of frame including FCS */
#ifndef _ASMLANGUAGE
/* types */
/* typedefs */
/* Receive Buffer Descriptor Header */
typedef struct _RXBUF_HDR
{
UINT32 adrs; /* receive buffer address */
UINT32 status; /* status */
} RXBUF_HDR;
/* Transmit Buffer Descriptor Header */
typedef struct _TXBUF_HDR
{
char * pAdrs; /* transmit buffer address */
int length; /* length of buffer */
BOOL inUse; /* buffer is used */
} TXBUF_HDR;
/* The definition of the driver control structure */
typedef struct _EMAC_END_DEVICE
{
END_OBJ end; /* The class we inherit from. */
int unit; /* unit number */
int ivec; /* interrupt vector */
int ilevel; /* interrupt level */
long flags; /* Our local flags. */
UCHAR enetAddr[6]; /* ethernet address */
CACHE_FUNCS * pCacheFuncs; /* cache function pointers */
CL_POOL_ID pClPoolId; /* cluster pool */
BOOL rxHandling; /* rcv task is scheduled */
volatile UINT32 * rxCluster; /* cluster addresses if used */
volatile UCHAR * rxBuff; /* base address of RX buffers */
volatile RXBUF_HDR * rxHdrs ; /* receive buffer descriptors */
int rxNum; /* number of RX buffers */
int rxIndex; /* index into the receive queue */
volatile TXBUF_HDR * txHdrs ; /* transmit buffer descriptors */
int txNum; /* number of TX buffers */
int txIndexWr; /* current index of available descriptor (put in TX queue) */
int txIndexRd; /* current index of packet to transmit (get from TX queue) */
char * pTxPollBuf; /* poll TX buffer */
} EMAC_END_DEVICE;
/* function declarations */
#if defined(__STDC__) || defined(__cplusplus)
IMPORT END_OBJ* at91EmacEndLoad (char* initString);
#else
IMPORT END_OBJ* at91EmacEndLoad ();
#endif /* __STDC__ */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* __INCat91EmacEndh */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -