📄 rominit.s
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MVN r1, #0 /* &FFFFFFFF */
STR r1, [r2, #AIC_IDCR] /* disable all FIQ sources */
STR r1, [r2, #AIC_ICCR] /* disable all IRQ sources */
/*
* Perform 8 End of Interrupt Commands as well, to ensure that
* no interrupt is stacked, leaving the hardware stack in the
* interrupt controller unbalanced.
*/
MOV r1, #8
1:
STR r1, [r2, #AIC_EOICR]
SUBS r1, r1, #1
BPL 1b
/* jump to the end if warmboot is performed */
TSTS r0, #BOOT_COLD /* is it a cold boot */
BEQ ClearDone /* branch if not */
/* switch to slow clock (if not already in) */
LDR r2, =AT91C_BASE_PMC
LDR r3,[r2,#PMC_MCKR]
CMP r3,#0
BEQ slowClock
/* clear PRES first */
BIC r3,r3,#PMC_MCKR_PRES_MASK
STR r3,[r2,#PMC_MCKR] /* PMC_MCKR &= ~PMC_MCKR_PRES_MASK */
/* then clear CSS */
LDR r3,[r2,#PMC_MCKR]
BIC r3,r3,#PMC_MCKR_CSS_MASK
STR r3,[r2,#PMC_MCKR] /* PMC_MCKR &= ~PMC_MCKR_CSS_MASK */
slowClock:
MOV r3,#0
loop1:
ADD r3,r3,#1
CMP r3,#99
BLE loop1
/* turn on the main oscillator an wait 50 ms (~400 slow clocks) */
MOV r3,#PMC_MOR_MOSCEN
STR r3,[r2,#PMC_MOR] /* PMC_MOR = 1 */
MOV r3,#0
loop2:
ADD r3,r3,#1
CMP r3,#400
BLE loop2
/* enable PLLA for 184.32 MHz (3.6864 Main/2 * 100) */
LDR r3, =CSB337_PLLA_VAL
STR r3,[r2,#PMC_PLLAR]
/* wait for PLLA lock bit */
MOV r3,#0
LDR r4,=1000
loop3:
ADD r3,r3,#1
CMP r3,#99
BLE loop3
/* set MCK to desired value */
LDR r3,=CSB337_PMC_MCKR_VAL
STR r3,[r2,#PMC_MCKR]
MOV r3,#0
LDR r1,=1000
loop4:
ADD r3,r3,#1
CMP r3,r1
BLE loop4
/* enable system clocks, PCK0, MCK and core clock */
LDR r3,=PMC_PCK0
STR r3,[r2,#PMC_SCER]
/* enable the clocks to all on-chip peripherals */
LDR r3,=CSB337_PMC_PCER_VAL
STR r3,[r2,#PMC_PCER]
MOV r3,#0
MOV r1,#1000
loop5:
ADD r3,r3,#1
CMP r3,r1
BLE loop5
/* set PCKO to PLLA/4 */
MOV r3,#(PMC_PCKR_PRES_4 | PMC_PCKR_CSS_PLLA)
STR r3,[r2,#PMC_PCKR0]
/* initialize SDRAM controller */
/* Assign SDRAMCS to CS1, all others to sram */
LDR r2,=AT91C_BASE_EBI
LDR r3,=EBI_CSA_CS1_SDRAM
STR r3,[r2,#EBI_CSA]
/* Disable databus D0-D15 pullups and bus sharing */
MOV r3,#0
STR r3,[r2,#EBI_CFGR]
/* Write sdram configuration register */
LDR r1,=LOCAL_MEM_LOCAL_ADRS /* index to SDRAM */
LDR r2,=AT91C_BASE_SDRAMC /* index to SDRAM Controller */
LDR r3,=CSB337_SDRAMC_CR_VAL /* for tmp value */
MOV r4,#0 /* for SDRAM access */
STR r3,[r2,#SDRAMC_CR]
/* Issue 2 nop's */
MOV r3,#SDRAMC_MR_NOP
STR r3,[r2,#SDRAMC_MR]
STR r4,[r1] /* write to SDRAM (2x) */
STR r4,[r1]
/* delay */
MOV r3,#0
loop6:
ADD r3,r3,#1
CMP r3,#99
BLE loop6
/* Issue precharge all */
MOV r3,#SDRAMC_MR_PRE
STR r3,[r2,#SDRAMC_MR]
STR r4,[r1] /* write to SDRAM */
/* delay */
MOV r3,#0
loop7:
ADD r3,r3,#1
CMP r3,#99
BLE loop7
/* Issue 8 refresh cycles */
MOV r3,#SDRAMC_MR_REF
STR r3,[r2,#SDRAMC_MR]
MOV r3,#0
refreshCycle:
STR r4,[r1] /* write to SDRAM */
ADD r3,r3,#1
CMP r3,#7
BLE refreshCycle
/* delay */
MOV r3,#0
loop8:
ADD r3,r3,#1
CMP r3,#99
BLE loop8
/* Issue mode register set */
MOV r3,#SDRAMC_MR_MRS
STR r3,[r2,#SDRAMC_MR]
STR r4,[r1,#0x80] /* write to SDRAM at offset 0x80 */
/* Set normal mode */
MOV r3,#SDRAMC_MR_NORM
STR r3,[r2,#SDRAMC_MR]
STR r4,[r1] /* write to SDRAM */
/* Set refresh */
MOV r3,#0x200
STR r3,[r2,#SDRAMC_TR]
STR r4,[r1] /* write to SDRAM */
/*
* Jump to the normal (higher) ROM Position. After a reset, the
* ROM is mapped into memory from location zero upwards as well
* as in its normal position at This code could be executing in
* the lower position. We wish to be executing the code, still
* in ROM, but in its normal (higher) position before we remap
* the machine so that the ROM is no longer dual-mapped from zero
* upwards, but so that RAM appears from 0 upwards.
*/
LDR r1, L$_HiPosn /* to check with the emulator what is loaded into PC */
LDR pc, L$_HiPosn /* <=> mov pc,r1 */
HiPosn:
/*
* The standard BSP startup code will clear the off-chip RAM,
* but will not clear the on-chip RAM. Clear it here now.
*/
TSTS r0, #BOOT_CLEAR /* should we clear RAM? */
BEQ ClearDone /* branch if not */
MOV sp, #0 /* clear from 0 upwards */
MOV r1, #0
MOV r2, #0
MOV r3, #0
MOV r4, #0
MOV r5, #0
MOV r6, #0
MOV r7, #0
MOV r8, #0
MOV r9, #AT91C_ISRAM_SIZE
MOV r13, #AT91C_ISRAM
5:
STMIA r13!,{r1-r8}
SUBS r9, r9, #32 /* clear 8 words of 4 bytes at a time */
BPL 5b /* branch if not all done */
ClearDone:
/*
* End of DRAM initialisation.
*
* Initialize the stack pointer to just before where the
* uncompress code, copied from ROM to RAM, will run.
*/
LDR sp, L$_STACK_ADDR
MOV fp, #0 /* zero frame pointer */
/* jump to C entry point in ROM: routine - entry point + ROM base */
LDR pc, L$_rStrtInRom
nop
/******************************************************************************/
/*
* PC-relative-addressable pointers - LDR Rn,=sym is broken
* note "_" after "$" to stop preprocessor performing substitution
*/
.balign 4
L$_HiPosn:
.long ROM_TEXT_ADRS + HiPosn - FUNC(romInit)
L$_rStrtInRom:
.long ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)
L$_STACK_ADDR:
.long STACK_ADRS
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