target.nr

VxWorks BSP for AT91RM92

'\" t
.so wrs.an
.\" csb337/target.nr - Cogent CSB337 target specific documentation
.\"
.\" Copyright 1984-2004 Wind River Systems, Inc.
.\"
.\" modification history
.\" --------------------
.\" 01b,14oct04,pdr  Updated BSP VTS results.
.\" 01a,06oct04,pdr  based on template target.nr.
.\"
.TH "csb337" T "Cogent CSB337" "Rev: 06 Oct 04" "TORNADO REFERENCE: VXWORKS"

.SH "NAME"
.aX "Cogent CSB337"

.SH "INTRODUCTION"
This reference entry provides board-specific information necessary to run
VxWorks for the CSB337 with an AT91RM9200 CPU (ARM920T core module).
Before using a board with VxWorks, verify that the board runs in the factory
configuration by using vendor-supplied ROMs and jumper settings and checking
the RS-232 connection.

.SS "Boot ROMs"
The boot ROM image has been tested running from Flash.  The Makefile
options are set to run the image from the start of Flash, 0x10000000.

At the time of this writing the following boot ROM images have been tested:

.TS E
expand;
cf3 s
lf3 lf3
l l .
.ne 5
Boot ROM Images
.sp .25
_
'bootrom' | - compressed VxWorks boot ROM image
'bootrom_uncmp' | - uncompressed VxWorks boot ROM image
'vxWorks_rom' | - uncompressed standalone VxWorks image with symbol table
.TE


To load VxWorks, and for more information, follow the instructions in the
.I "Tornado User's Guide: Getting Started."

.SS "Jumpers"
Does not apply.


.SH "FEATURES"
The CSB337 is a Single Board Computer with an Atmel AT91RM9200 CPU. Based upon the
ARM920T Core, the CSB337 provides a development platform.

List of features of the CSB337 board:

	- 180Mhz Atmel AT91RM9200 (ARM920T core)
	- ARM920T I-Cache (16 KByte)
	- ARM920T D-Cache (16 KByte)
	- Advanced Interrupt Controller (AIC) with 32 sources
	- 16 KBytes internal SRAM
	- 128 KBytes internal ROM
	- External Bus Interface (EBI)
	- Debug Unit (DBGU) with a two-wire UART
	- Ethernet MAC 10/100 Base-T (EMAC) with LXT971A PHY
	- USB Host port (UHP)
	- USB Device port (UDP)
	- Multimedia Card Interface (MCI)
	- 3 x Synchonous Serial Controller (SCC)
	- 4 x Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
	- Master/Slave Peripheral Interface (SPI)
	- 2 x 3 16-bit Timer/Counter (TC)
	- Two-Wire Interface (TWI)
	- 32Mbyte 32-Bit Wide SDRAM (Micron MT48LC8M16-7TG or equivalent)
	- 8Mbyte 16-Bit Wide Intel 28F640J3A (or equivalent) StrataFLASH
	- Epson S1D13706 320x240 LCD Controller with Internal 80K Frame Buffer
	- Dallas DS1307 (or 3.3V equivalent DS1338) Real Time Clock With 56Byte NVRAM
	- Infineon SAK82C900 Dual CAN Controller via SPI
	- Secure Digital (SD) Card Socket via Internal SDIO Controller (4-Bit)
	- Compact Flash Interface (socket provided on User Board)
	- I2S Codec Interface via GPIO Expansion Connector
	- JTAG Debug Interface (ARM)
	- User Readable 4 Position DIP Switch
   
.SS "Supported Features"
List of features of the CSB337 board:

	- 180Mhz Atmel AT91RM9200 (ARM920T core)
	- ARM920T I-Cache (16 KByte)
	- ARM920T D-Cache (16 KByte)
	- Advanced Interrupt Controller (AIC)
	- 16 KBytes internal SRAM
	- 128 KBytes internal ROM
	- External Bus Interface (EBI)
	- Debug Unit (DBGU) with a two-wire UART (-> Serial 0)
	- Ethernet MAC 10/100 Base-T (EMAC) with LXT971A PHY
	- 1 x Universal Synchronous/Asynchronous Receiver/Transmitter (USART) (-> Serial 1)
	- 2 16-bit Timer/Counter (TC) (TC0 and TC1)
	- 32Mbyte 32-Bit Wide SDRAM (Micron MT48LC8M16-7TG or equivalent)
	- 8Mbyte 16-Bit Wide Intel 28F640J3A (or equivalent) StrataFLASH

.SS "RAM size"
The RAM size is configured by changing LOCAL_MEM_SIZE in config.h.  If this
is reduced below 8 MBytes, other values may need changing, such as
RAM_HIGH_ADRS.

.SS "Internal ROM/SRAM"
After reset the SRAM is only accessible at address 0x200000 until
the remap command. After Remap, the SRAM is also available at address 0x0.
At any time the internal ROM is mapped at address 0x100000. It is also
accessible at address 0x0 after reset and before the Remap Command if the
Boot Mode Select (BMS) is tied high during reset.

.SS "Timestamp support"
Two of the on-chip timers (channels 0 and 1) are used by the system and
auxiliary clock facilities.  The system clock provides the timestamp
timer as well.

.SS "Flash memory as NVRAM"
If the BSP is configured with INCLUDE_FLASH defined, the standard VxWorks
Flash support is included.  The last sector of the boot flash is configured
to be used as NVRAM.
	
.SS "Interrupt controller"
If AT91_INT_USE_PROTECT_MODE is defined (the default), then the Protect
Mode feature of the interrupt controller is also used, allowing the
interrupt vector registers to be read by debuggers.  See the
documentation for at91IntDevInit() for further details.
	
.SS "Unsupported Features"
List of unsupported features of the CSB337 board:

	- USB Host port (UHP)
	- USB Device port (UDP)
	- Multimedia Card Interface (MCI)
	- 3 x Synchonous Serial Controller (SCC)
	- 2 x 3 16-bit Timer/Counter (TC)
	- Two-Wire Interface (TWI)
	- Epson S1D13706 320x240 LCD Controller with Internal 80K Frame Buffer
	- Dallas DS1307 (or 3.3V equivalent DS1338) Real Time Clock With 56Byte NVRAM
	- Infineon SAK82C900 Dual CAN Controller via SPI
	- Secure Digital (SD) Card Socket via Internal SDIO Controller (4-Bit)
	- Compact Flash Interface (socket provided on User Board)
	- I2S Codec Interface via GPIO Expansion Connector
	- User Readable 4 Position DIP Switch (connected as GPIOs via SAK82C900)

.SS "Fast Interrupt (FIQ)"
Fast Interrupt (FIQ) is not handled byVxWorks. BSPs can use FIQ as they wish, but
VxWorks code should not be called from FIQ handlers.

.SS "Feature Interactions"
The JTAG Debug Interface (ARM) does not need software support from the BSP.


.SH "HARDWARE DETAILS"
This section documents the details of the device drivers and board
hardware elements.

.SS "Devices"
The chip drivers included in this BSP are:

    at91Timer.c - AT91 timer driver (system/auxiliary/timestamp clock)
    at91Sio.c - AT91 SIO driver
    flashMem.c - generic flash library
    nvRamToFlash.c - byte-oriented generic non-volatile RAM library
    nullVme.c - null VMEbus library
    at91IntrCtl.c - AT91RM9200 interrrupt controller device
    at91EmacEnd.c - AT91RM9200 END driver

.SS "Memory Maps"
.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l l .
.ne 5
ARM920T MMU areas
.sp .25
start and end address | : MMU, Cache setting | : Description
_
0x0000'0000--0x003f'ffff | : valid, read-write, uncached    | : SRAM, ROM, USB Host (internal Memory) (4 MB)
0x1000'0000--0x107f'ffff | : valid, read-write, uncached    | : Flash (8 MB)
0x2000'0000--0x21ff'ffff | : valid, read-write, cache       | : SDRAM (32 MB)
0xfffa'ffff--0xffff'ffff | : valid, read-write, uncached    | : User and System peripheral (6 MB)
.TE


.SS "Shared Memory"
Does not apply.

.SS "Interrupts"
32 interrupt levels are provided:

    0 Fast Interrupt (FIQ)
    1 System Peripherals (DBGU, ST, SDRAMC, RTC, PMC)
    2 Parallel I/O Controller A
    3 Parallel I/O Controller B
    4 Parallel I/O Controller C
    5 Parallel I/O Controller D
    6 USART 0
    7 USART 1
    8 USART 2
    9 USART 3
   10 Multimedia Card Interface
   11 USB Device Port
   12 Two-Wire Interface
   13 Serial Peripheral Interface
   14 Synchronous Serial Controller 0
   15 Synchronous Serial Controller 0
   16 Synchronous Serial Controller 0
   17 Timer/Counter 0
   18 Timer/Counter 1
   19 Timer/Counter 2
   20 Timer/Counter 3
   21 Timer/Counter 4
   22 Timer/Counter 5
   23 USB Host Port
   24 Ethernet MAC
   25 IRQ0
   26 IRQ1
   27 IRQ2
   28 IRQ3
   29 IRQ4
   30 IRQ5
   31 IRQ6

Only interrupt levels 6, 17, 18 and 24 are used by default
in this BSP.  Interrupt connection, enabling and disabling are
performed using the standard intArchLib routines.  The interrupt
controller driver is provided in at91IntrCtl.c.

Level 1 is managed through dedicated routines (see "Special Routines" section below)
For Level 1, the following ID should be used for the special routines:

   0  Real Time Clock (RTC)
   1  System Timer (ST)
   2  Debug Unit (DBGU)
   3  Power Management Controller (PMC)
   4  Memory Controller (MC)


.SS "Serial Configuration"
There are two serial ports on the board, one serial line is used as
Console (Serial 1) and is provided through USART1 interface.
The second (Serial 0) is provided by the DBGU interface.

The default configuration is 38400 baud, 8 data bits, no parity, 1 stop bit,
no flow control.

.SS "SCSI Configuration"
Does not apply.

.SS "Network Configuration"
This BSP provides network support for integrate Ethernet MAC controller (EMAC).

The enhanced network driver (END) interface name is defined as "emac".
The unit number is zero (0).  The MAC address of the
interface can be set using sysEnetAddrSet().  For further information, see the
reference entry for this routine.

.I Note:
The MAC address is stored in NVRAM after the bootline parameter. When no MAC address is
stored the default MAC address (00:23:31:37:01:61) will be used.

.I Note:
The first three bytes of the MAC address contain a fixed manufacturer's code.
This code is defined by ENET_DEFAULT in config.h.

.I Note:
Ethernet Address can be specified at the bootrom prompt (N command).
The Ethernet address is stored in the on board NVRAM.
This option will able  you to change the last three bytes. To use 
this option, open the console window (for example: hyper terminal) and when 
the bootrom banner appear and the countdown start, press any key, when you get 
the [VxWorks Boot] prompt , press 'N' and follow the instructions.

.SS "VME Access"
Does not apply.

.SS "PCI Access"
Does not apply.

.SS "Boot Devices"
The supported boot device is:

    \f3emac\f1 - Ethernet (10/100baseT)

The BSP does support Ethernet boot over the Ethernet interface 'emac',
and standalone ROM VxWorks images only.


.SS "Boot Methods"
For booting only FTP network and VxWorks standalone ROM image support has been
tested.  bootp, proxy-arp, tftp, rsh, etc. may still work.

.SS "ROM Considerations"
This section will guide you step by step how to get vxWorks running on this 
board.

.CS
1. Setting the board Jumpers & Switches: