csb337.h

VxWorks BSP for AT91RM92

/* csb337.h - csb337 board header */

/* Copyright 2004 Wind River Systems, Inc. */

/*
modification history
--------------------
01a,07sep04,pdr  written
*/

/*
This file contains I/O address and related constants for the CSB337.
*/


#ifndef	INCcsb337h
#define	INCcsb337h

#ifdef __cplusplus
extern "C" {
#endif

#include "at91rm9200.h"

#define TARGET_CSB337


#define BUS		BUS_TYPE_NONE		/* No PCI, VME etc. */

/* BSP memory map */

#define CSB337_PERIPHERAL_BASE	0xFFFA0000
#define CSB337_PERIPHERAL_SIZE	0x00600000  /* */

/* 
 * CS0 configuration: Flash
 * NWS: 10 wait states
 * WSEN: wait states enaled
 * TDF: Data Flat Time = 1 cycle
 * BAT: Byte Access Type CS is 16 bit
 * DBW: Data Bus Width is 16 bit
 * DRP: standard read protocol
 * ACSS: Address to chip select setup is standard
 * RWSETUP: Read and Write Signal Setup Time 1,5 cycle
 * RWHOLD: Read and Write Signal Hold Time 1 cycle
 */
#define CSB337_CS0_VAL 	    ( 0x1100318A )

/* CS1 configuration: reserved for SDRAMC */
#define CSB337_CS1_VAL 	    ( 0x00002000 )

/* CS2 configuration: Epson S1D13706 (not supported) */
#define CSB337_CS2_VAL 	    ( 0x00002000 )

/* CS3 configuration: Expansion Chip Select 0 (not supported) */
#define CSB337_CS3_VAL 	    ( 0x00002000 )

/* CS4 configuration: Compact Flash Chip Enable 1 (not supported) */
#define CSB337_CS4_VAL 	    ( 0x00002000 )

/* CS5 configuration: Compact Flash Chip Enable 1 (not supported) */
#define CSB337_CS5_VAL 	    ( 0x00002000 )

/* CS6 configuration: Compact Flash Chip Enable 2 (not supported) */
#define CSB337_CS6_VAL 	    ( 0x00002000 )

/* CS7 configuration: Expansion Chip Select 1 (not supported) */
#define CSB337_CS7_VAL 	    ( 0x00002000 )

/* 
 * PMC Clock PLLA Register Configuration
 * MULA = 0x63 (99) ->  clock*(MULA+1)
 * OUTA = 10b       -> 150 MHz < pllaout < 240 MHz
 * PLLA = 0x3e (62) -> counter for LOCKA bit (slow clock cycles)
 * DIVA = 2         -> clock/2
 *
 * pllaout = clock * (MULA+1) / DIVA => 3.6864 MHz * 100 / 2 = 184.32 MHz
 */
#define CSB337_PLLA_VAL         0x2063be02 /* 0x20633e02 */


/* 
 * Main clock is used (3.6864 MHz)
 * CPU Clock = 4 * Master Clock 
 */
#define CSB337_PMC_MCKR_VAL     0x0302

/* on-chip peripheral clock enable */
#define CSB337_PMC_PCER_VAL     0x01fffffc

/* SDRAM settings */
#define CSB337_SDRAMC_CR_VAL    0x2188B0D5


/* Signals generated from BSP clock generator. */

#define CSB337_CPU_SPEED        184320000               /* 184.32 MHz MCLK speed */
#define CSB337_MCLK_SPEED	    (CSB337_CPU_SPEED/4)	/* The timer speed is related to this (46.08 MHz) */

/*
 * interrupt control stuff
 * Note: FIQ is not handled within VxWorks so this is just IRQ
 */


#define AT91_INT_NUM_LEVELS	32			/* enable IRQ interrupts levels */

/* definitions in form used by interrupt driver */

#define AT91_INT_CSR_MODE	AT91C_AIC_SMR	/* Source Mode register */
#define AT91_INT_CSR_SVEC	AT91C_AIC_SVR	/* Source Vector register */
#define AT91_INT_CSR_VECT	AT91C_AIC_IVR	/* Interrupt vector register */
#define AT91_INT_CSR_PEND	AT91C_AIC_IPR	/* Interrupt pending register */
#define AT91_INT_CSR_IMR	AT91C_AIC_IMR	/* Interrupt Mask register */
#define AT91_INT_CSR_ENB	AT91C_AIC_IECR	/* Interrupt Enable register */
#define AT91_INT_CSR_DIS	AT91C_AIC_IDCR	/* Interrupt Disable register */
#define AT91_INT_CSR_EOIC	AT91C_AIC_EOICR	/* End-of-Interrupt Command reg*/
#define AT91_INT_CSR_SPU	AT91C_AIC_SPU	/* Spurious Vector register */


/* interrupt levels (= Peripheral ID) */

#define INT_LVL_SYS     	AT91C_ID_SYS	/* System */
#define INT_LVL_SERIAL_0	AT91C_ID_SYS	/* System - DBGU is used as Serial 0 */
#define INT_LVL_SERIAL_1	AT91C_ID_US1	/* USART 1 */
#define INT_LVL_TIMER_0		AT91C_ID_TC0	/* Timer 0 */
#define INT_LVL_TIMER_1		AT91C_ID_TC1	/* Timer 1 */
#define INT_LVL_TIMER_2		AT91C_ID_TC2	/* Timer 2 */
#define INT_LVL_ETH		    AT91C_ID_EMAC	/* Ethernet (EMAC) */

/* peripheral system definition */
#define SP_RTC_ID       0   /* Real Time Clock */
#define SP_ST_ID        1   /* System Timer */
#define SP_DBGU_ID      2   /* Debug Unit */
#define SP_PMC_ID       3   /* Power Management Controller */
#define SP_MC_ID        4   /* Memory Controller */
#define SP_MAX_ID       5   



/* interrupt priority */

#define INT_PRI_SERIAL_0	3	/* Serial 0 - DBGU */
#define INT_PRI_SERIAL_1	2	/* Serial 1 - USART1 */
#define INT_PRI_TIMER_0		6	/* Timer 0  - System Tick*/
#define INT_PRI_TIMER_1		5	/* Timer 1  - Auxiliary clock*/
#define INT_PRI_TIMER_2		0	/* Timer 2 */
#define INT_PRI_ETH		    7	/* Ethernet (EMAC) */

/* interrupt vectors */

#define INT_VEC_SYS	        IVEC_TO_INUM(INT_LVL_SYS)	    /* System Peripheral */
#define INT_VEC_SERIAL_0	IVEC_TO_INUM(INT_LVL_SERIAL_0)	/* SERIAL 0 - DBGU */
#define INT_VEC_SERIAL_1	IVEC_TO_INUM(INT_LVL_SERIAL_1)	/* SERIAL 1 - USART1 */
#define INT_VEC_TIMER_0	    IVEC_TO_INUM(INT_LVL_TIMER_0)	/* Timer 0 */
#define INT_VEC_TIMER_1	    IVEC_TO_INUM(INT_LVL_TIMER_1)	/* Timer 1 */
#define INT_VEC_TIMER_2	    IVEC_TO_INUM(INT_LVL_TIMER_2)	/* Timer 2 */
#define INT_VEC_ETH	        IVEC_TO_INUM(INT_LVL_ETH)	    /* Watchdog timer */


/* definitions for the UART */

/* definitions for SIO driver */

#define N_AT91_USART_CHANNELS	2
#define N_SIO_CHANNELS		    N_AT91_USART_CHANNELS


/* system/auxiliary clock definitions */

#define SYS_TIMER_INT_LVL (INT_LVL_TIMER_0)
#define AUX_TIMER_INT_LVL (INT_LVL_TIMER_1)
#define SYS_TIMER_INT_VEC (INT_VEC_TIMER_0)
#define AUX_TIMER_INT_VEC (INT_VEC_TIMER_1)

/* Frequency of counter/timers */

#define SYS_TIMER_CLK	(CSB337_MCLK_SPEED/128)
#define AUX_TIMER_CLK	(CSB337_MCLK_SPEED/128)

/*
 * Clock rates depend upon CPU power and work load of application.
 * The values below are minimum and maximum allowed by the hardware.
 * So:
 * min frequency = roundup(clock_rate/(max_counter_value))
 * max frequency = rounddown(clock_rate/(min_counter_value))
 * i.e. SYS_CLK_RATE_MAX = SYS_TIMER_CLK
 *      AUX_CLK_RATE_MAX = AUX_TIMER_CLK
 *
 * However, we must set maxima that are sustainable on a running
 * system determined by experimentation.
 *
 * The 720T values have been determined by experimentation, the others
 * need to be checked.
 */

#define SYS_CLK_RATE_MIN    ((SYS_TIMER_CLK+0xFFFF)/0x10000)
#define SYS_CLK_RATE_MAX    25000

#define AUX_CLK_RATE_MIN    ((AUX_TIMER_CLK+0xFFFF)/0x10000)
#define AUX_CLK_RATE_MAX    25000

/* Definitions for LED controller and sysLedsReadWrite */

#define USRLED0		    0x04    /* PB2 */
#define USRLED1		    0x02    /* PB1 */
#define USRLED2		    0x01    /* PB0 */

#define LED_LEDS_MASK	0x07

/* Handy sizes */

#define SZ_1K                           0x00000400
#define SZ_4K                           0x00001000
#define SZ_8K                           0x00002000
#define SZ_16K                          0x00004000
#define SZ_64K                          0x00010000
#define SZ_128K                         0x00020000
#define SZ_256K                         0x00040000
#define SZ_512K                         0x00080000

#define SZ_1M                           0x00100000
#define SZ_2M                           0x00200000
#define SZ_4M                           0x00400000
#define SZ_8M                           0x00800000
#define SZ_16M                          0x01000000
#define SZ_32M                          0x02000000
#define SZ_64M                          0x04000000
#define SZ_128M                         0x08000000
#define SZ_256M                         0x10000000
#define SZ_512M                         0x20000000

#define SZ_1G                           0x40000000
#define SZ_2G                           0x80000000


#ifdef __cplusplus
}
#endif

#endif	/* INCcsb337h */