nco.map.qmsg

用VHDL语言写好得

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 12 21:44:38 2006 " "Info: Processing started: Tue Dec 12 21:44:38 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off NCO -c NCO --analyze_file=F:\\nco\\NCO.vhd " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off NCO -c NCO --analyze_file=F:\\nco\\NCO.vhd" {  } {  } 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"type\" NCO.vhd(7) " "Error: VHDL syntax error at NCO.vhd(7) near text \"type\"" {  } { { "F:/nco/NCO.vhd" "" "" { Text "F:/nco/NCO.vhd" 7 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "std_logic NCO.vhd(27) " "Error: VHDL error at NCO.vhd(27): object std_logic is used but not declared" {  } { { "F:/nco/NCO.vhd" "" "" { Text "F:/nco/NCO.vhd" 27 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "std_logic NCO.vhd(28) " "Error: VHDL error at NCO.vhd(28): object std_logic is used but not declared" {  } { { "F:/nco/NCO.vhd" "" "" { Text "F:/nco/NCO.vhd" 28 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "std_logic_vector NCO.vhd(29) " "Error: VHDL error at NCO.vhd(29): object std_logic_vector is used but not declared" {  } { { "F:/nco/NCO.vhd" "" "" { Text "F:/nco/NCO.vhd" 29 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "std_logic NCO.vhd(31) " "Error: VHDL error at NCO.vhd(31): object std_logic is used but not declared" {  } { { "F:/nco/NCO.vhd" "" "" { Text "F:/nco/NCO.vhd" 31 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "std_logic_vector NCO.vhd(32) " "Error: VHDL error at NCO.vhd(32): object std_logic_vector is used but not declared" {  } { { "F:/nco/NCO.vhd" "" "" { Text "F:/nco/NCO.vhd" 32 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "nco_data NCO.vhd(34) " "Error: VHDL error at NCO.vhd(34): object nco_data is used but not declared" {  } { { "F:/nco/NCO.vhd" "" "" { Text "F:/nco/NCO.vhd" 34 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_UNIT_INGONRED_ERR" "addr_sin NCO.vhd(23) " "Error: Ignored construct addr_sin at NCO.vhd(23) because of previous errors" {  } { { "F:/nco/NCO.vhd" "" "" { Text "F:/nco/NCO.vhd" 23 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_UNCOMPILED_ENTITY" "addr_sin NCO.vhd(40) " "Error: VHDL error at NCO.vhd(40): entity addr_sin is used but not declared" {  } { { "F:/nco/NCO.vhd" "" "" { Text "F:/nco/NCO.vhd" 40 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "std_logic_vector NCO.vhd(43) " "Error: VHDL error at NCO.vhd(43): object std_logic_vector is used but not declared" {  } { { "F:/nco/NCO.vhd" "" "" { Text "F:/nco/NCO.vhd" 43 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "dout NCO.vhd(48) " "Error: VHDL error at NCO.vhd(48): object dout is used but not declared" {  } { { "F:/nco/NCO.vhd" "" "" { Text "F:/nco/NCO.vhd" 48 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "a_sin NCO.vhd(54) " "Error: VHDL error at NCO.vhd(54): object a_sin is used but not declared" {  } { { "F:/nco/NCO.vhd" "" "" { Text "F:/nco/NCO.vhd" 54 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "g_sin NCO.vhd(53) " "Error: VHDL error at NCO.vhd(53): object g_sin is used but not declared" {  } { { "F:/nco/NCO.vhd" "" "" { Text "F:/nco/NCO.vhd" 53 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "g_sin NCO.vhd(50) " "Error: VHDL error at NCO.vhd(50): object g_sin is used but not declared" {  } { { "F:/nco/NCO.vhd" "" "" { Text "F:/nco/NCO.vhd" 50 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "data_con_sin NCO.vhd(50) " "Error: VHDL error at NCO.vhd(50): object data_con_sin is used but not declared" {  } { { "F:/nco/NCO.vhd" "" "" { Text "F:/nco/NCO.vhd" 50 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "a_siny NCO.vhd(63) " "Error: VHDL error at NCO.vhd(63): object a_siny is used but not declared" {  } { { "F:/nco/NCO.vhd" "" "" { Text "F:/nco/NCO.vhd" 63 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "g_siny NCO.vhd(62) " "Error: VHDL error at NCO.vhd(62): object g_siny is used but not declared" {  } { { "F:/nco/NCO.vhd" "" "" { Text "F:/nco/NCO.vhd" 62 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "g_siny NCO.vhd(59) " "Error: VHDL error at NCO.vhd(59): object g_siny is used but not declared" {  } { { "F:/nco/NCO.vhd" "" "" { Text "F:/nco/NCO.vhd" 59 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "data_con_siny NCO.vhd(59) " "Error: VHDL error at NCO.vhd(59): object data_con_siny is used but not declared" {  } { { "F:/nco/NCO.vhd" "" "" { Text "F:/nco/NCO.vhd" 59 0 0 } }  } 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 19 s 0 s " "Error: Quartus II Analysis & Synthesis was unsuccessful. 19 errors, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Tue Dec 12 21:44:39 2006 " "Error: Processing ended: Tue Dec 12 21:44:39 2006" {  } {  } 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}