nco.vhd

用VHDL语言写好得

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;


type NCO_data is range 0.000000 to 1.000000;
--entity addr_sin is
--    Port(clock :         in  STD_LoGIC;          --时钟信号
--         reset :         in  STD_LoGIC;          --同步复位信号
          --定义频率控制字寄存器
--         g_sin :         in  STD_LoGIC;
--         data_con_sin :  in  STD_LoGIC_VECToR(31 downto o);
--         d_con_sin :     out STD_LoGIC_VECToR(31 downto 0);
         --定义相位控制字寄存器
--         g_sinl :        in  STD_LOGIC;
  --       data_con_sinl ：in  STD_LOGIC_VECTOR(31 downto 0);
--         d_con_sin1 :    out std_logic_vector(31 downto 0);
--         dout :          out STD_LoGIC_VECToR(15 downto 0)--加法器输出信号
--);
--end addr_sin;

ENTITY addr_sin IS

	PORT
	(
		clock ,reset    : IN    STD_LOGIC;
		g_sin		    : IN	STD_LOGIC;
		data_con_sin	: IN	STD_LOGIC_VECTOR(31 DOWNTO 0);
		--d_con_sin    	: OUT	STD_LOGIC_VECTOR(31 DOWNTO 0);
		g_siny		    : IN	STD_LOGIC;
		data_con_siny	: IN	STD_LOGIC_VECTOR(31 DOWNTO 0);
		---d_con_siny    	: OUT	STD_LOGIC_VECTOR(31 DOWNTO 0);
		y            	: OUT	NCO_data
	);
END addr_sin;



architecture Behavioral of addr_sin is

--定义中间变量并初始化
    signal a_sin,a_siny,count,county,dout : STD_LOGIC_VECTOR(31 downto 0) :="00000000000000000000000000000000";   
    begin

    --d_con_sin  <= a_sin;   --用于微处理器读频率控制字寄存器
    --d_con_siny <= a_siny;  --用于微处理器读相位控制字寄存器
    dout <= county (31 downto 16);--加法器输出

    process(g_sin,data_con_sin)--写频率控制字寄存器
    begin
       
       if(g_sin='1') then
          a_sin <= data_con_sin;--
       end if;
    end process;


    process(g_siny,data_con_siny)--写相位控制字寄存器
    begin

      if(g_siny='1') then
         a_siny <= data_con_siny;
      end if;
    end process;


    process(clock,reset)--加法器输出逻辑
    begin

       if reset='1' then
          count  <= "00000000000000000000000000000000";--累加器清零
          county <= "00000000000000000000000000000000";--加法器清零   
       elsif(clock='1' and clock'event) then
          count  <= count+a_sin;    --累加器输出
          county <= count+a_siny;    --加法器输出
       end if;
    end process;

    process(dout)
    begin
       case dout(31 downto 16) is
            when "00000000000000" => y <= 0.000000 ;	
            when "00000000000001" => y <= 0.002109 ;	
	

            when others => y <= 1  ;
       end case;


    end process;







end Behavioral;