count.vhd

VHDL to System C translator

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--                                                                           --
--  VH2SC example file                                                       --
--                                                                           --
--  Contact/Feedback : http://www.ht-lab.com/feedback.htm                    --
--  Web: http://www.ht-lab.com                                               --
--                                                                           --
-------------------------------------------------------------------------------
library IEEE;                           -- All IEEE library clause are
use IEEE.std_logic_1164.all;            -- ignored
use IEEE.std_logic_unsigned.all;

entity cnt is                           -- Note the filename is count.vhd, however
                                        -- the generated files are cnt.cpp and cnt.h!
                                        -- use -oh or -oc to change the filename to
                                        -- for example count.cpp and count.h
    port (
        clk         : in std_logic ;    -- std_logic is converter to SystemC type bool
        reset       : in std_logic ;    -- std_logic_vector is converter to sc_uint<>
        updown      : in std_logic ;    -- inout/buffer ports are not supported.
        count       : out std_logic_vector(2 downto 0)); 
end cnt;

architecture rtl of cnt is

    signal count_s : std_logic_vector(2 downto 0);

    -- pragma vh2sc_off                 -- Use pragma vh2sc_on/off to ignore non-supported
                                        -- code constructs. translate_on/off and synthesis_on/off
                                        -- are also supported.
    alias   cflagin   : std_logic is count_s(2);-- Not supported
    -- pragma vh2sc_on


begin

    process (reset, clk)                -- simple counter, converted into SC_METHOD
                                        -- process is not named, vh2sc will use process_line37
        begin                           -- for the resulting function name.
            if (reset = '1') then
                count_s <= (others => '0');
            elsif (rising_edge(clk)) then
                if (updown = '1') then
                    count_s <= count_s + '1' ;
                else 
                    count_s <= count_s - '1' ;
                end if ;
            end if ;
            							-- assertions and reports are supported
            assert NOT (count_s=7) report "Counter Overflow" severity failure;

    end process ;

    count <= count_s;                   -- converted to a separate "combinatorial" SC_METHOD
                                        -- process. Note large amount of combinatorial code 
                                        -- could reduce performance.
end rtl ;