count_tb.vhd

来自「VHDL to System C translator」· VHDL 代码 · 共 68 行

-------------------------------------------------------------------------------
--                                                                           --
--  VH2SC example file                                                       --
--                                                                           --
--  Contact/Feedback : http://www.ht-lab.com/feedback.htm                    --
--  Web: http://www.ht-lab.com                                               --
--                                                                           --
-------------------------------------------------------------------------------
-- count up to 14, count down to 0 count up to 15                            --
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity count_tb is
end entity count_tb;

architecture behaviour of count_tb is

component cnt is
    port (
        clk         : in std_logic ;
        reset       : in std_logic ;
        updown      : in std_logic ;
        count       : out std_logic_vector(2 downto 0));
end component cnt;

    signal clk_s        : std_logic ;
    signal reset_s      : std_logic ;
    signal updown_s     : std_logic ;
    signal count_s      : std_logic_vector(2 downto 0);

begin
    dut : cnt
        port map (clk => clk_s,
                  reset => reset_s,
                  updown => updown_s,
                  count => count_s);


    process             --  generate Clock
        variable c:std_logic :='1';
        begin
            c := not c;
            clk_s <= c;  
            wait for 100 ns;
    end process;
 
    process
        begin         
                    
            reset_s <= '1';         
            updown_s <= '1';  
            wait until rising_edge(clk_s);             
            reset_s  <= '0';
            for i in 0 to 5 loop
                wait until rising_edge(clk_s);
            end loop;
            updown_s <= '0';
            for i in 0 to 6 loop
                wait until rising_edge(clk_s);
            end loop;
            wait;

    end process;

end architecture;