aes_top_tester.vhd

VHDL to System C translator

-------------------------------------------------------------------------------
--                                                                           --
--  AES86 - VHDL 128bits AES IP Core                                         --
--  Copyright (C) 2005-2007 HT-LAB                                           --
--                                                                           --
--  Contact/Feedback : http://www.ht-lab.com/feedback.htm                    --
--  Web: http://www.ht-lab.com                                               --
--                                                                           --
--  AES86 is released as open-source under the GNU GPL license. This means   --
--  that designs based on AES86 must be distributed in full source code      --
--  under the same license. Contact HT-Lab for commercial applications where --
--  source-code distribution is not desirable.                               --
--                                                                           --
-------------------------------------------------------------------------------
--                                                                           --
--  This library is free software; you can redistribute it and/or            --
--  modify it under the terms of the GNU Lesser General Public               --
--  License as published by the Free Software Foundation; either             --
--  version 2.1 of the License, or (at your option) any later version.       --
--                                                                           --
--  This library is distributed in the hope that it will be useful,          --
--  but WITHOUT ANY WARRANTY; without even the implied warranty of           --
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        --
--  Lesser General Public License for more details.                          --
--                                                                           --
--  Full details of the license can be found in the file "copying.txt".      --
--                                                                           --
--  You should have received a copy of the GNU Lesser General Public         --
--  License along with this library; if not, write to the Free Software      --
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA  --
--                                                                           --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
LIBRARY std;
USE std.TEXTIO.all;

ENTITY AES_ecb_top_tester IS
   PORT( 
      clk        : IN     std_logic;
      data_valid : IN     std_logic;
      dout       : IN     std_logic_vector (127 DOWNTO 0);
      key_valid  : IN     std_logic;
      resetn     : IN     std_logic;
      din        : OUT    std_logic_vector (127 DOWNTO 0);
      enc_dec    : OUT    std_logic;
      ld_data    : OUT    std_logic;
      ld_key     : OUT    std_logic
   );

-- Declarations

END AES_ecb_top_tester ;

--
ARCHITECTURE behaviour OF AES_ecb_top_tester IS

function std_to_hex(Vec : std_logic_vector) return string is
    constant L       : natural := Vec'length;
    alias MyVec      : std_logic_vector(L - 1 downto 0) is Vec;
    constant LVecFul : natural := ((L - 1)/4 + 1)*4;
    variable VecFul  : std_logic_vector(LVecFul - 1 downto 0) 
                                    := (others => '0');
    constant StrLgth : natural := LVecFul/4;
    variable Res     : string(1 to StrLgth) := (others => ' ');
    variable TempVec : std_logic_vector(3 downto 0);
    variable i       : integer := LVecFul - 1;
    variable Index   : natural := 1;
  begin
    assert L > 1 report "(std_to_hex) requires a vector!" severity error;
    
    VecFul(L - 1 downto 0) := MyVec(L -1 downto 0);
    
    while (i - 3 >= 0) loop
      TempVec(3 downto 0) := VecFul(i downto i - 3);
      case TempVec(3 downto 0) is
         when "0000" => Res(Index) := '0';
         when "0001" => Res(Index) := '1';
         when "0010" => Res(Index) := '2';
         when "0011" => Res(Index) := '3';
         when "0100" => Res(Index) := '4';
         when "0101" => Res(Index) := '5';
         when "0110" => Res(Index) := '6';
         when "0111" => Res(Index) := '7';
         when "1000" => Res(Index) := '8';
         when "1001" => Res(Index) := '9';
         when "1010" => Res(Index) := 'A';
         when "1011" => Res(Index) := 'B';
         when "1100" => Res(Index) := 'C';
         when "1101" => Res(Index) := 'D';
         when "1110" => Res(Index) := 'E';
         when "1111" => Res(Index) := 'F';
         when others => Res(Index) := 'x';
      end case; -- TempVec(3 downto 0) 
      Index := Index + 1;
      i := i - 4;
    end loop;
    
    return Res;
    
end std_to_hex;


signal key_s: std_logic_vector(127 downto 0);
signal dout_s: std_logic_vector(127 downto 0);

BEGIN
  	process
  		variable L : line; -- used for monitor

		  begin
			
					   
			wait for 10 ns;
			
			enc_dec <='0';
			ld_key  <= '0';	
			ld_data <= '0';	

			key_s  <= (others=> '0');
			dout_s <= (others=> '0');
			din    <= (others=> '0');

            wait until rising_edge(resetn);
            wait until rising_edge(clk);
            			                
            -- ***********************************************************************************
            --  Expand First key for Encryption
            -- ***********************************************************************************
            
            wait for 10 ns;									-- Expand Key
            din <= key_s;	 								-- Load Key
            ld_key  <= '1';
            wait until rising_edge(clk);
            wait until rising_edge(clk);					-- Need to hold ld_key and data for 3 clock cycles!!
            wait until rising_edge(clk);				   
            
            wait for 5 ns; -- hold time			  
            ld_key  <= '0';
            din <= (others => 'Z');	 						-- Tri-state bus
            wait until key_valid='1';  		  	   
            wait until rising_edge(clk);

            enc_dec <='0';

            write(L,string'("Note: This testbench may take several hours to complete!"));	
			writeline(output,L);
			write(L,string'("Note: To complete the Monte Carlo Test, the AES core is iterated 8 million times!"));	
			writeline(output,L);

			-- ***********************************************************************************
			--  Start Encryption, 4Million cycles!
			-- ***********************************************************************************

			write(L,string'("****** Start Monte Carlo AES Encrypt test ******"));
			writeline(output,L);

	  	   	for i in 0 to 39 loop 							-- 399
            
	            write(L,string'("I="));write(L,i);			-- Write Iteration number
	            writeline(output,L);

				write(L,string'("Key="));					-- Write input key
				write(L,std_to_hex(key_s));
				writeline(output,L);

				write(L,string'("PT ="));					-- Write input data
				write(L,std_to_hex(dout_s));					
				writeline(output,L);

	            			
			   	for j in 0 to 9999 loop            			 							   
		            wait for 200 ns;						-- Encrypt Data
		            wait until rising_edge(clk);	
		            wait for 10 ns;   
		            din <= dout_s; 	  						-- feedback output back to input
		            ld_data <= '1';
		            wait until rising_edge(clk);			-- Need to hold ld_data and data 4 clock cycles!!
		            wait until rising_edge(clk);		
		            wait until rising_edge(clk);		
		            wait until rising_edge(clk);		
		            wait for 5 ns;							-- hold time
		            ld_data <= '0';
		            din <= (others => 'Z');	 				-- Tri-state bus
		            wait until data_valid='1';
					dout_s <= dout;							-- update data;
					wait until rising_edge(clk);

	            end loop;
	            		
	            write(L,string'("CT ="));					-- Write Encrypted data
	            write(L,std_to_hex(dout_s));					
	            writeline(output,L);
            			  
				-- Next XOR the key and output result -> load new key
				-- Data out -> Data in
			   	key_s <= key_s XOR dout;
				dout_s <= dout;								 -- temp copy

				wait for 10 ns;								 -- Expand Key
				din <= key_s;	 							 -- Load New Key
				ld_key  <= '1';
				wait until rising_edge(clk);
				wait until rising_edge(clk);				 -- Need to hold ld_key and data 3 clock cycles!!
				wait until rising_edge(clk);					

				wait for 5 ns; -- hold time			  
				ld_key  <= '0';
				din <= (others => 'Z');	 					 -- Tri-state bus
				wait until key_valid='1';  		  	   
				wait until rising_edge(clk);
		   
	 	end loop;

		assert FALSE report "************** End of Test **************" severity FAILURE;
	  	wait;

	  end process;
END ARCHITECTURE behaviour;