aes_ecb_top_tb.vhd

VHDL to System C translator

-------------------------------------------------------------------------------
--                                                                           --
--  AES86 - VHDL 128bits AES IP Core                                         --
--  Copyright (C) 2005-2007 HT-LAB                                           --
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--  AES86 is released as open-source under the GNU GPL license. This means   --
--  that designs based on AES86 must be distributed in full source code      --
--  under the same license. Contact HT-Lab for commercial applications where --
--  source-code distribution is not desirable.                               --
--                                                                           --
-------------------------------------------------------------------------------
--                                                                           --
--  This library is free software; you can redistribute it and/or            --
--  modify it under the terms of the GNU Lesser General Public               --
--  License as published by the Free Software Foundation; either             --
--  version 2.1 of the License, or (at your option) any later version.       --
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--  This library is distributed in the hope that it will be useful,          --
--  but WITHOUT ANY WARRANTY; without even the implied warranty of           --
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        --
--  Lesser General Public License for more details.                          --
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--  Full details of the license can be found in the file "copying.txt".      --
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--  You should have received a copy of the GNU Lesser General Public         --
--  License along with this library; if not, write to the Free Software      --
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA  --
--                                                                           --
-------------------------------------------------------------------------------

ENTITY AES_ecb_top_tb IS
END AES_ecb_top_tb ;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
LIBRARY std;
USE std.TEXTIO.all;


ARCHITECTURE struct OF AES_ecb_top_tb IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL clk        : std_logic;
   SIGNAL data_valid : std_logic;
   SIGNAL din        : std_logic_vector(127 DOWNTO 0);
   SIGNAL dout       : std_logic_vector(127 DOWNTO 0);
   SIGNAL enc_dec    : std_logic;
   SIGNAL key_valid  : std_logic;
   SIGNAL ld_data    : std_logic;
   SIGNAL ld_key     : std_logic;
   SIGNAL resetn     : std_logic;


   -- ModuleWare signal declarations(v1.6) for instance 'I2' of 'clk'
   SIGNAL mw_I2clk : std_logic;

   -- ModuleWare signal declarations(v1.6) for instance 'I3' of 'pulse'
   SIGNAL mw_I3pulse : std_logic :='0';

   -- Component Declarations
   COMPONENT AES_ecb_top
   PORT (
      clk        : IN     std_logic ;
      din        : IN     std_logic_vector (127 DOWNTO 0);
      enc_dec    : IN     std_logic ;
      ld_data    : IN     std_logic ;
      ld_key     : IN     std_logic ;
      resetn     : IN     std_logic ;
      busy       : OUT    std_logic ;
      data_valid : OUT    std_logic ;
      dout       : OUT    std_logic_vector (127 DOWNTO 0);
      key_valid  : OUT    std_logic 
   );
   END COMPONENT;
   COMPONENT AES_ecb_top_tester
   PORT (
      clk        : IN     std_logic ;
      data_valid : IN     std_logic ;
      dout       : IN     std_logic_vector (127 DOWNTO 0);
      key_valid  : IN     std_logic ;
      resetn     : IN     std_logic ;
      din        : OUT    std_logic_vector (127 DOWNTO 0);
      enc_dec    : OUT    std_logic ;
      ld_data    : OUT    std_logic ;
      ld_key     : OUT    std_logic 
   );
   END COMPONENT;


BEGIN

   -- ModuleWare code(v1.6) for instance 'I2' of 'clk'
   i2clk_proc: PROCESS
   BEGIN
      LOOP
         mw_I2clk <= '0', '1' AFTER 50 ns;
         WAIT FOR 100 ns;
      END LOOP;
      WAIT;
   END PROCESS i2clk_proc;
   clk <= mw_I2clk;

   -- ModuleWare code(v1.6) for instance 'I3' of 'pulse'
   resetn <= mw_I3pulse;
   i3pulse_proc: PROCESS
   BEGIN
      WAIT FOR 50 ns;
      mw_I3pulse <= 
         '0',
         '1' AFTER 200 ns;
      WAIT;
    END PROCESS i3pulse_proc;

   -- Instance port mappings.
   I0 : AES_ecb_top
      PORT MAP (
         clk        => clk,
         din        => din,
         enc_dec    => enc_dec,
         ld_data    => ld_data,
         ld_key     => ld_key,
         resetn     => resetn,
         busy       => OPEN,
         data_valid => data_valid,
         dout       => dout,
         key_valid  => key_valid
      );
   I1 : AES_ecb_top_tester
      PORT MAP (
         clk        => clk,
         data_valid => data_valid,
         dout       => dout,
         key_valid  => key_valid,
         resetn     => resetn,
         din        => din,
         enc_dec    => enc_dec,
         ld_data    => ld_data,
         ld_key     => ld_key
      );

END struct;