fsm.vhd

VHDL to System C translator

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-------------------------------------------------------------------------------
                                               
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


ENTITY fsm IS
   PORT( 
      clk   : IN     std_logic;
      reset : IN     std_logic; -- Active low reset
      start : IN     std_logic;
      cnt   : IN     std_logic_vector (4 DOWNTO 0);
      init  : OUT    std_logic;
      load  : OUT    std_logic;
      done  : OUT    std_logic);
END fsm ;


architecture synthesis of fsm is
         
 type   states is (s0,s1,s2,s3);
 signal state,nextstate : states;     

begin
         
 Process (clk,reset)      -- Process to create current state variables 
  begin
   if (reset='0') then       -- Reset State
       state <= s0;              
   elsif (rising_edge(clk)) then   
       state <= nextstate;   -- Set Current state
   end if;   
 end process;  
   
 process(state,start,cnt)
  begin  
   case state is
      when s0 =>                               -- Step 1 load regs
           if  start='1' then nextstate <= s1; 
                         else nextstate <= s0; -- Wait for start signal 
           end if; 
           
      when s1 =>                               -- latch result register
           if  cnt="11111" then nextstate <= s2; -- done
                             else nextstate <= s1; -- wait
           end if;                            
           
      when s2 =>                                                                              
           if  start='0' then nextstate <= s0; 
                         else nextstate <= s2; -- Wait for start signal 
           end if; 
           
      when others => nextstate <= s0;              
   end case;                   
 end process;    
 
 process(state)
  begin  
   case state is
      when s0 =>done <= '0'; init <= '1'; load <= '0';                                                   
      when s1 =>done <= '0'; init <= '0'; load <= '1';    
      when s2 =>done <= '1'; init <= '0'; load <= '0';           
      when others => done <= '-'; init <= '-'; load <= '-';               
   end case;                   
 end process;  

end synthesis;