cordic.vhd

VHDL to System C translator

-------------------------------------------------------------------------------
--                                                                           --
--  Simple Cordic                                                            --
--  Copyright (C) 1999 HT-LAB                                                --
--                                                                           --
--  Contact/Feedback : http://www.ht-lab.com/feedback.htm                    --
--  Web: http://www.ht-lab.com                                               --
--                                                                           --
-------------------------------------------------------------------------------
--                                                                           --
--  This library is free software; you can redistribute it and/or            --
--  modify it under the terms of the GNU Lesser General Public               --
--  License as published by the Free Software Foundation; either             --
--  version 2.1 of the License, or (at your option) any later version.       --
--                                                                           --
--  This library is distributed in the hope that it will be useful,          --
--  but WITHOUT ANY WARRANTY; without even the implied warranty of           --
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        --
--  Lesser General Public License for more details.                          --
--                                                                           --
--  Full details of the license can be found in the file "copying.txt".      --
--                                                                           --
--  You should have received a copy of the GNU Lesser General Public         --
--  License along with this library; if not, write to the Free Software      --
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA  --
--                                                                           --
-------------------------------------------------------------------------------
-- Cordic Top                                                                --
--                                                                           --
-- Simple SIN/COS Cordic example                                             --
-- 32 bits fixed format Sign,2^0, 2^-1,2^-2 etc.                             --
-- angle input +/-0.5phi                                                     --
--                                                                           --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

use work.cordic_pkg.all;

entity cordic is    
   port(clk    : in  std_logic;                    
        reset  : in  std_logic;                     -- Active low reset
        angle  : in  std_logic_vector(31 downto 0); -- input radian 
        sin    : out std_logic_vector(31 downto 0); 
        cos    : out std_logic_vector(31 downto 0);       
        start  : in  std_logic; 
        done   : out std_logic);              
end cordic;


architecture synthesis of cordic is
        
    signal cnt_s  : std_logic_vector(4 downto 0); -- bit counter, 2^5

    signal newx_s : std_logic_vector(31 downto 0);
    signal newy_s : std_logic_vector(31 downto 0);
    signal newz_s : std_logic_vector(31 downto 0);

    signal xreg_s : std_logic_vector(31 downto 0);
    signal yreg_s : std_logic_vector(31 downto 0);
    signal zreg_s : std_logic_vector(31 downto 0);

    signal sxreg_s: std_logic_vector(31 downto 0);
    signal syreg_s: std_logic_vector(31 downto 0);

    signal atan_s : std_logic_vector(31 downto 0); -- arctan LUT

    signal init_s : std_logic;
    signal load_s : std_logic;
    signal as_s   : std_logic;
    signal nas_s  : std_logic;
 
begin
 
    SHIFT1: shiftn  port map (xreg_s,sxreg_s,cnt_s);
    SHIFT2: shiftn  port map (yreg_s,syreg_s,cnt_s);

    nas_s <= not as_s;
    ADD1  : addsub  port map (xreg_s,syreg_s,newx_s,as_s);   -- xreg
    ADD2  : addsub  port map (yreg_s,sxreg_s,newy_s,nas_s);  -- yreg

    LUT   : atan32 port map(cnt_s,atan_s);

    ADD3  : addsub port map (zreg_s,atan_s(31 downto 0),newz_s,as_s);    -- zreg

    FSM1  : fsm port map (clk,reset,start,cnt_s,init_s,load_s,done); 
 
 -- COS(X) Register
    process (clk,newx_s) 
    begin
        if (rising_edge(clk)) then
           if init_s='1' then xreg_s(31 downto 0) <= xinit_c; -- fails in vh2sc xinit_c(31 downto 0); -- 0.607     
           elsif load_s='1' then xreg_s <= newx_s;                   
           end if;
        end if;   
    end process;   

 -- SIN(Y) Register
    process (clk,newy_s) 
    begin
        if (rising_edge(clk)) then
           if init_s='1' then yreg_s <= yinit_c; -- 0.0000    fails  in vh2sc yinit_c(31 downto 0)
           elsif load_s='1' then yreg_s <= newy_s;                   
           end if;
        end if;   
    end process;   

    -- Z Register
    process (clk,newz_s,angle) 
    begin
        if (rising_edge(clk)) then
           if init_s='1' then zreg_s <= angle;          -- x
           elsif load_s='1' then zreg_s <= newz_s;                   
           end if;
        end if;   
    end process;   

    as_s <= zreg_s(31); -- MSB=Sign bit   

    process (clk,load_s,init_s) -- bit counter
    begin
        if (rising_edge(clk)) then   
           if init_s='1' then cnt_s<=(others=> '0');
            elsif (load_s='1') then cnt_s <= cnt_s + '1';
           end if;   
        end if;   
    end process; 

    sin  <= yreg_s;
    cos  <= xreg_s;

end synthesis;