addsub.vhd

VHDL to System C translator

-------------------------------------------------------------------------------
--                                                                           --
--  Simple Cordic                                                            --
--  Copyright (C) 1999 HT-LAB                                                --
--                                                                           --
--  Contact/Feedback : http://www.ht-lab.com/feedback.htm                    --
--  Web: http://www.ht-lab.com                                               --
--                                                                           --
-------------------------------------------------------------------------------
--                                                                           --
--  This library is free software; you can redistribute it and/or            --
--  modify it under the terms of the GNU Lesser General Public               --
--  License as published by the Free Software Foundation; either             --
--  version 2.1 of the License, or (at your option) any later version.       --
--                                                                           --
--  This library is distributed in the hope that it will be useful,          --
--  but WITHOUT ANY WARRANTY; without even the implied warranty of           --
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        --
--  Lesser General Public License for more details.                          --
--                                                                           --
--  Full details of the license can be found in the file "copying.txt".      --
--                                                                           --
--  You should have received a copy of the GNU Lesser General Public         --
--  License along with this library; if not, write to the Free Software      --
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA  --
--                                                                           --
-------------------------------------------------------------------------------
-- Adder/Subtracter                                                          --
-- no overflow.                                                              --
--                                                                           --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity addsub is
    port (abus   : in  std_logic_vector(31 downto 0);
          bbus   : in  std_logic_vector(31 downto 0);
          obus   : out std_logic_vector(31 downto 0);         
          as     : in  std_logic);          --add=1, subtract=0          
end addsub;

architecture synthesis of addsub is

begin

  process(as,abus,bbus)
    begin
      if as='1' then 
         obus <= abus + bbus;
      else
         obus <= abus - bbus;
    end if;        
  end process;  
      
end synthesis;