atan32.vhd

VHDL to System C translator

-------------------------------------------------------------------------------
--                                                                           --
--  Simple Cordic                                                            --
--  Copyright (C) 1999 HT-LAB                                                --
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-------------------------------------------------------------------------------
--                                                                           --
--  This library is free software; you can redistribute it and/or            --
--  modify it under the terms of the GNU Lesser General Public               --
--  License as published by the Free Software Foundation; either             --
--  version 2.1 of the License, or (at your option) any later version.       --
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--  This library is distributed in the hope that it will be useful,          --
--  but WITHOUT ANY WARRANTY; without even the implied warranty of           --
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        --
--  Lesser General Public License for more details.                          --
--                                                                           --
--  Full details of the license can be found in the file "copying.txt".      --
--                                                                           --
--  You should have received a copy of the GNU Lesser General Public         --
--  License along with this library; if not, write to the Free Software      --
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA  --
--                                                                           --
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity atan32 is
  port ( za    : in std_logic_vector(4 downto 0);
         zdata : out std_logic_vector(31 downto 0));
end atan32;


Architecture synthesis of atan32 Is
Begin
  process(ZA)
  begin
    Case ZA is	                           
       when "00000" => ZData <= X"3243f6a8";
       when "00001" => ZData <= X"1dac6705";
       when "00010" => ZData <= X"0fadbafc";
       when "00011" => ZData <= X"07f56ea6";
       when "00100" => ZData <= X"03feab76";
       when "00101" => ZData <= X"01ffd55b";
       when "00110" => ZData <= X"00fffaaa";
       when "00111" => ZData <= X"007fff55";
       when "01000" => ZData <= X"003fffea";
       when "01001" => ZData <= X"001ffffd";
       when "01010" => ZData <= X"000fffff";
       when "01011" => ZData <= X"0007ffff";
       when "01100" => ZData <= X"0003ffff";
       when "01101" => ZData <= X"0001ffff";
       when "01110" => ZData <= X"0000ffff";
       when "01111" => ZData <= X"00007fff";
       when "10000" => ZData <= X"00003fff";
       when "10001" => ZData <= X"00001fff";
       when "10010" => ZData <= X"00000fff";
       when "10011" => ZData <= X"000007ff";
       when "10100" => ZData <= X"000003ff";
       when "10101" => ZData <= X"000001ff";
       when "10110" => ZData <= X"000000ff";
       when "10111" => ZData <= X"0000007f";
       when "11000" => ZData <= X"0000003f";
       when "11001" => ZData <= X"0000001f";
       when "11010" => ZData <= X"0000000f";
       when "11011" => ZData <= X"00000007";
       when "11100" => ZData <= X"00000003";
       when "11101" => ZData <= X"00000001";
       when "11110" => ZData <= X"00000000";
       when "11111" => ZData <= X"00000000";
       When others  => ZData <= "--------------------------------";
    end case;
  end process;
end synthesis;