📄 filtref.map.rpt
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Analysis & Synthesis report for filtref
Mon Nov 12 22:39:09 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Messages
6. Analysis & Synthesis Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Failed - Mon Nov 12 22:39:09 2007 ;
; Quartus II Version ; 7.1 Build 156 04/30/2007 SJ Full Version ;
; Revision Name ; filtref ;
; Top-level Entity Name ; filtref ;
; Family ; APEX20KE ;
+-----------------------------+------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------------------------------+--------------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------------------------------+--------------+---------------+
; Top-level entity name ; filtref ; filtref ;
; Family name ; APEX20KE ; Stratix II ;
; Optimization Technique -- APEX 20K/APEX 20KE/APEX 20KC/APEX II/ARM-based Excalibur ; Speed ; Balanced ;
; Carry Chain Length ; 32 ; 48 ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Auto Implement in ROM ; Off ; Off ;
; Technology Mapper -- APEX 20K/APEX 20KE/APEX 20KC/APEX II/ARM-based Excalibur ; LUT ; LUT ;
; Allow XOR Gate Usage ; On ; On ;
; Cascade Chain Length ; 2 ; 2 ;
; Parallel Expander Chain Length -- APEX 20K/APEX 20KE/APEX 20KC/APEX II/ARM-based Excalibur ; 16 ; 16 ;
; Auto Carry Chains ; On ; On ;
; Auto Parallel Expanders ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Use smart compilation ; Off ; Off ;
+--------------------------------------------------------------------------------------------+--------------+---------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+
; filtref.bdf ; yes ; User Block Diagram/Schematic File ; E:/新建文件夹 (2)/Altare公司训练新人的练习题/Lab1/filtref.bdf ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Mon Nov 12 22:39:07 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off filtref -c filtref
Info: Found 1 design units, including 1 entities, in source file taps.v
Info: Found entity 1: taps
Info: Found 1 design units, including 1 entities, in source file acc.v
Info: Found entity 1: acc
Info: Found 1 design units, including 1 entities, in source file accum.v
Info: Found entity 1: accum
Info: Found 1 design units, including 1 entities, in source file filtref.bdf
Info: Found entity 1: filtref
Info: Found 1 design units, including 1 entities, in source file hvalues.v
Info: Found entity 1: hvalues
Info: Found 1 design units, including 1 entities, in source file state_m.v
Info: Found entity 1: state_m
Info: Elaborating entity "filtref" for the top level hierarchy
Error: Can't find mapping for conduit in block of type taps of instance "inst1"
Error: Can't find mapping for conduit in block of type hvalues of instance "inst"
Error: Can't find mapping for conduit in block of type acc of instance "inst4"
Error: Can't elaborate top-level user hierarchy
Info: Generated suppressed messages file E:/新建文件夹 (2)/Altare公司训练新人的练习题/Lab1/filtref.map.smsg
Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 0 warnings
Info: Allocated 132 megabytes of memory during processing
Error: Processing ended: Mon Nov 12 22:39:09 2007
Error: Elapsed time: 00:00:02
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in E:/新建文件夹 (2)/Altare公司训练新人的练习题/Lab1/filtref.map.smsg.
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