control.vqm

Altare公司用于训练新人的练习题

//
// Written by Synplify
// Thu May 10 09:13:51 2001
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\d:\!projects\launch_team\logiclock\control\pipe_mult.v "
// file 2 "\d:\!projects\launch_team\logiclock\control\control.v "

module pipe_mult (
  ctrl_data_mux_reg_2,
  ctrl_data_mux_reg_1,
  ctrl_data_mux_reg_0,
  ctrl_data_mux_reg_3,
  ctrl_data_mux_reg_4,
  filter_data_mux_reg_3,
  filter_data_mux_reg_0,
  filter_data_mux_reg_4,
  filter_data_mux_reg_2,
  filter_data_mux_reg_1,
  filter_data_mux_reg_5,
  filter_data_mux_reg_13,
  filter_data_mux_reg_6,
  filter_data_mux_reg_14,
  filter_data_mux_reg_7,
  filter_data_mux_reg_15,
  filter_data_mux_reg_8,
  filter_data_mux_reg_12,
  filter_data_mux_reg_9,
  filter_data_mux_reg_11,
  filter_data_mux_reg_10,
  ctrl_out_0,
  ctrl_out_1,
  ctrl_out_2,
  ctrl_out_3,
  ctrl_out_4,
  ctrl_out_5,
  ctrl_out_6,
  ctrl_out_7,
  ctrl_out_8,
  ctrl_out_9,
  ctrl_out_10,
  ctrl_out_11,
  ctrl_out_12,
  ctrl_out_13,
  ctrl_out_14,
  ctrl_out_15,
  ctrl_out_16,
  ctrl_out_17,
  ctrl_out_18,
  ctrl_out_19,
  ctrl_out_20,
  clk_ctrl
);
input ctrl_data_mux_reg_2;
input ctrl_data_mux_reg_1;
input ctrl_data_mux_reg_0;
input ctrl_data_mux_reg_3;
input ctrl_data_mux_reg_4;
input filter_data_mux_reg_3;
input filter_data_mux_reg_0;
input filter_data_mux_reg_4;
input filter_data_mux_reg_2;
input filter_data_mux_reg_1;
input filter_data_mux_reg_5;
input filter_data_mux_reg_13;
input filter_data_mux_reg_6;
input filter_data_mux_reg_14;
input filter_data_mux_reg_7;
input filter_data_mux_reg_15;
input filter_data_mux_reg_8;
input filter_data_mux_reg_12;
input filter_data_mux_reg_9;
input filter_data_mux_reg_11;
input filter_data_mux_reg_10;
output ctrl_out_0;
output ctrl_out_1;
output ctrl_out_2;
output ctrl_out_3;
output ctrl_out_4;
output ctrl_out_5;
output ctrl_out_6;
output ctrl_out_7;
output ctrl_out_8;
output ctrl_out_9;
output ctrl_out_10;
output ctrl_out_11;
output ctrl_out_12;
output ctrl_out_13;
output ctrl_out_14;
output ctrl_out_15;
output ctrl_out_16;
output ctrl_out_17;
output ctrl_out_18;
output ctrl_out_19;
output ctrl_out_20;
input clk_ctrl;
wire ctrl_data_mux_reg_2 ;
wire ctrl_data_mux_reg_1 ;
wire ctrl_data_mux_reg_0 ;
wire ctrl_data_mux_reg_3 ;
wire ctrl_data_mux_reg_4 ;
wire filter_data_mux_reg_3 ;
wire filter_data_mux_reg_0 ;
wire filter_data_mux_reg_4 ;
wire filter_data_mux_reg_2 ;
wire filter_data_mux_reg_1 ;
wire filter_data_mux_reg_5 ;
wire filter_data_mux_reg_13 ;
wire filter_data_mux_reg_6 ;
wire filter_data_mux_reg_14 ;
wire filter_data_mux_reg_7 ;
wire filter_data_mux_reg_15 ;
wire filter_data_mux_reg_8 ;
wire filter_data_mux_reg_12 ;
wire filter_data_mux_reg_9 ;
wire filter_data_mux_reg_11 ;
wire filter_data_mux_reg_10 ;
wire ctrl_out_0 ;
wire ctrl_out_1 ;
wire ctrl_out_2 ;
wire ctrl_out_3 ;
wire ctrl_out_4 ;
wire ctrl_out_5 ;
wire ctrl_out_6 ;
wire ctrl_out_7 ;
wire ctrl_out_8 ;
wire ctrl_out_9 ;
wire ctrl_out_10 ;
wire ctrl_out_11 ;
wire ctrl_out_12 ;
wire ctrl_out_13 ;
wire ctrl_out_14 ;
wire ctrl_out_15 ;
wire ctrl_out_16 ;
wire ctrl_out_17 ;
wire ctrl_out_18 ;
wire ctrl_out_19 ;
wire ctrl_out_20 ;
wire clk_ctrl ;
wire [20:0] ctrl_out;
wire [20:0] result_temp5;
wire [20:0] result_temp4;
wire [15:0] filter_data_mux_reg;
wire [4:0] ctrl_data_mux_reg;
wire [62:1] IF_width_inf_IF_width_inf_mult1_FirstStep_ab_0_and2_0_and2;
wire Z1_regsA_result_carry_15 ;
wire Z1_regsA_result_carry_14 ;
wire Z1_regsA_result_carry_13 ;
wire Z1_regsA_result_carry_12 ;
wire Z1_regsA_result_carry_11 ;
wire Z1_regsA_result_carry_10 ;
wire Z1_regsA_result_carry_9 ;
wire Z1_regsA_result_carry_8 ;
wire Z1_regsA_result_carry_7 ;
wire Z1_regsA_result_carry_6 ;
wire Z1_regsA_result_carry_5 ;
wire Z1_regsA_result_carry_4 ;
wire Z1_regsA_result_carry_3 ;
wire Z1_regsA_result_carry_2 ;
wire Z1_regsA_result_carry_1 ;
wire Z1_regsA_result_carry_0 ;
wire Z1_regsA_un183_result_carry_11 ;
wire Z1_regsA_un183_result_carry_10 ;
wire Z1_regsA_un183_result_carry_9 ;
wire Z1_regsA_un183_result_carry_15 ;
wire Z1_regsA_un183_result_carry_8 ;
wire I_161_cout ;
wire Z1_regsA_un183_result_carry_7 ;
wire Z1_regsA_un183_result_carry_14 ;
wire Z1_regsA_un183_result_carry_6 ;
wire Z1_regsA_un183_result_carry_13 ;
wire Z1_regsA_un183_result_carry_12 ;
wire Z1_regsA_un183_result_carry_5 ;
wire Z1_regsA_un183_result_carry_2 ;
wire Z1_regsA_un183_result_carry_1 ;
wire Z1_regsA_un183_result_carry_4 ;
wire Z1_regsA_un183_result_carry_3 ;
wire Z1_regsA_un183_result_carry_0 ;
wire Z2_regsA_un118_result_carry_11 ;
wire Z2_regsA_un118_result_carry_17 ;
wire Z2_regsA_un118_result_carry_10 ;
wire I_142_cout ;
wire Z2_regsA_un118_result_carry_9 ;
wire Z2_regsA_un118_result_carry_16 ;
wire Z2_regsA_un118_result_carry_8 ;
wire Z2_regsA_un118_result_carry_15 ;
wire Z2_regsA_un118_result_carry_7 ;
wire Z2_regsA_un118_result_carry_14 ;
wire Z2_regsA_un118_result_carry_6 ;
wire Z2_regsA_un118_result_carry_13 ;
wire Z2_regsA_un118_result_carry_12 ;
wire Z2_regsA_un118_result_carry_5 ;
wire Z2_regsA_un118_result_carry_2 ;
wire Z2_regsA_un118_result_carry_4 ;
wire Z2_regsA_un118_result_carry_3 ;
wire I_10 ;
wire I_74 ;
wire I_157 ;
wire I_134 ;
wire I_72 ;
wire Z1_regsA_un56_result_carry_11 ;
wire I_170 ;
wire I_147 ;
wire I_71 ;
wire Z1_regsA_un56_result_carry_17 ;
wire I_70 ;
wire Z1_regsA_un56_result_carry_10 ;
wire I_168 ;
wire I_145 ;
wire I_69 ;
wire I_69_cout ;
wire I_144 ;
wire I_68 ;
wire Z1_regsA_un56_result_carry_9 ;
wire I_166 ;
wire I_143 ;
wire I_67 ;
wire Z1_regsA_un56_result_carry_16 ;
wire I_142 ;
wire I_66 ;
wire Z1_regsA_un56_result_carry_8 ;
wire I_164 ;
wire I_141 ;
wire I_65 ;
wire Z1_regsA_un56_result_carry_15 ;
wire I_163 ;
wire I_140 ;
wire I_64 ;
wire Z1_regsA_un56_result_carry_7 ;
wire I_162 ;
wire I_139 ;
wire I_63 ;
wire Z1_regsA_un56_result_carry_14 ;
wire I_161 ;
wire I_138 ;
wire I_62 ;
wire Z1_regsA_un56_result_carry_6 ;
wire I_160 ;
wire I_137 ;
wire I_61 ;
wire Z1_regsA_un56_result_carry_13 ;
wire I_159 ;
wire I_136 ;
wire Z1_regsA_un56_result_carry_12 ;
wire I_60 ;
wire Z1_regsA_un56_result_carry_5 ;
wire I_158 ;
wire I_135 ;
wire I_59 ;
wire I_154 ;
wire I_131 ;
wire I_58 ;
wire I_152 ;
wire I_129 ;
wire Z1_regsA_un56_result_carry_2 ;
wire I_57 ;
wire Z1_regsA_un56_result_carry_1 ;
wire I_155 ;
wire I_132 ;
wire I_56 ;
wire Z1_regsA_un56_result_carry_4 ;
wire I_156 ;
wire I_133 ;
wire Z1_regsA_un56_result_carry_3 ;
wire I_55 ;
wire Z1_regsA_un56_result_carry_0 ;
wire I_153 ;
wire I_130 ;
wire I_50 ;
wire I_122 ;
wire I_49 ;
wire I_121 ;
wire I_48 ;
wire I_120 ;
wire I_47 ;
wire I_119 ;
wire I_46 ;
wire I_118 ;
wire I_45 ;
wire I_117 ;
wire I_44 ;
wire I_116 ;
wire I_43 ;
wire I_115 ;
wire I_42 ;
wire I_114 ;
wire I_41 ;
wire I_113 ;
wire I_40 ;
wire I_112 ;
wire I_39 ;
wire I_111 ;
wire I_38 ;
wire I_110 ;
wire I_37 ;
wire I_109 ;
wire I_36 ;
wire I_108 ;
wire I_34 ;
wire I_106 ;
wire I_32 ;
wire I_151 ;
wire I_31 ;
wire I_104 ;
wire I_15 ;
wire I_14 ;
wire I_11 ;
wire I_13 ;
wire I_16 ;
wire I_18 ;
wire I_20 ;
wire I_22 ;
wire I_24 ;
wire I_26 ;
wire I_25 ;
wire I_23 ;
wire I_8 ;
wire I_7 ;
wire I_21 ;
wire I_6 ;
wire I_12 ;
wire I_17 ;
wire I_19 ;
wire I_9 ;
wire GND ;
wire VCC ;
//@1:1
  assign VCC = 1'b1;
//@1:1
  assign GND = 1'b0;
// @255:31