config_controller.v

采用CPLD来培植ALTERA公司的CYCLONE系列FPGA

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//-- Title		: config_controller.v                               	     	--
//-- Modified	: 04/09/2005                                                 	--
//-- Author		: Altera Component Applications                                 -- 
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//-- Description: 	This design allows for configuration from multiple pages     
//--              	with either the Stratix PGM pins (remote/local) or the Dipswitch (MPGM pins)
//--				as the page select source(non-remote/local). 
//--				It can configure stratix II board. Some customization of the code is required 
//--				in order to work on specified board. Please refer to below description.
//-- 
//-- Note:
//-- 1.	This design has some additional features beyond what is described in the note.                                
//-- 2.	When max_en is '1' the MAX device will NOT attempt to configure the device
//-- 3.	All LEDs indication board specific, user can customize or comment out the "LED_DRIVER" portion of code.
//-- 4. User has to define the flash start address based on user system requirement. Refer to "User defined page start address" portion of code
//-- 5. User has to define the flash address width in the header.v file based on system requirement. 
//-- 6. In PS mode, fpga_DATA(7 downto 1) is not required. (user can remove this pin in other configuration mode)	   
//-- 7. In PPA mode, fpga_DCLK is not required. (user can remove this pin in other configuration mode)	   
//-- 8.	fpga_CS, fpag_nCS, fpga_nWS and fpga_nRS is only required in PPA mode. (user can remove this pin in other configuration mode)	 
//-- 9. If "Enable INIT_DONE Output" option is turn on in QII, define "INIT_DONE" in "header.v" file
//--10. "INIT_DCLK_CNT" parameter is the additonal DCLK signal after the configuration cycle. Refer to "Number of additional DCLK count after Configuration" in header.v file.
//--
//--
//--Refer to documentation for details on functionality of this design.                       
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//--Copyright