📄 hardware_reg.h
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/********************************************************************************************
*filename: hardware_reg.h
*author: willhua
*create date: 2003-7-14 14:17
*description: This file defined registers of all the module
*modify history:
*misc:
********************************************************************************************/
#ifndef _HARWARE_REG_H
#define _HARWARE_REG_H
#include "HA_typedef.h"
//#define FPGA
/***************************************************
define INTC registers
***************************************************/
#ifdef FPGA
#define BASE_INTC 0x40000000
#else
#define BASE_INTC 0x10000000
#endif
#define INTC_IEN ( BASE_INTC+0X0 )
#define INTC_IMSK ( BASE_INTC+0X8 )
#define INTC_IFCE ( BASE_INTC+0X10 )
#define INTC_IRSTAT ( BASE_INTC+0X18 )
#define INTC_ISTAT ( BASE_INTC+0X20 )
#define INTC_IMSTAT ( BASE_INTC+0X28 )
#define INTC_IFSTAT ( BASE_INTC+0X30 )
#define INTC_FEN ( BASE_INTC+0XC0 )
#define INTC_FMSK ( BASE_INTC+0XC4 )
#define INTC_FFCE ( BASE_INTC+0XC8 )
#define INTC_FRSTAT ( BASE_INTC+0XCC )
#define INTC_FSTAT ( BASE_INTC+0XD0 )
#define INTC_FFSTAT ( BASE_INTC+0XD4 )
#define INTC_PLV ( BASE_INTC+0XD8 )
/*************************************************
define GPT registers
*************************************************/
#ifdef FPGA
#define GPT_BASE 0x40006000
#else
#define GPT_BASE 0x10003000
#endif
#define GPT1_COMP (GPT_BASE + 0x00)
#define GPT1_CNT (GPT_BASE + 0x04)
#define GPT1_CNTL (GPT_BASE + 0x08)
#define GPT1_EOI (GPT_BASE + 0x0c)
#define GPT1_IST (GPT_BASE + 0x10)
#define GPT2_COMP (GPT_BASE + 0x14)
#define GPT2_CNT (GPT_BASE + 0x18)
#define GPT2_CNTL (GPT_BASE + 0x1C)
#define GPT2_EOI (GPT_BASE + 0x20)
#define GPT2_IST (GPT_BASE + 0x24)
#define GPT3_COMP (GPT_BASE + 0x28)
#define GPT3_CNT (GPT_BASE + 0x2C)
#define GPT3_CNTL (GPT_BASE + 0x30)
#define GPT3_EOI (GPT_BASE + 0x34)
#define GPT3_IST (GPT_BASE + 0x38)
#define GPT4_COMP (GPT_BASE + 0x3C)
#define GPT4_CNT (GPT_BASE + 0x40)
#define GPT4_CNTL (GPT_BASE + 0x44)
#define GPT4_EOI (GPT_BASE + 0x48)
#define GPT4_IST (GPT_BASE + 0x4C)
#define GPT_GLB_EOI (GPT_BASE + 0XA0)
#define GPT_GLB_IST (GPT_BASE + 0XA4)
#define GPT_GLB_RIST (GPT_BASE + 0XA8)
/************************************************
define PWM registers
************************************************/
#ifdef FPGA
#define PWM_BASE 0x40007000
#else
#define PWM_BASE 0x1000C000
#endif
#define PWM1_CNTL (PWM_BASE + 0X00)
#define PWM1_S (PWM_BASE + 0X04)
#define PWM1_P (PWM_BASE + 0X08)
#define PWM1_CNT (PWM_BASE + 0X0C)
#define PWM2_CNTL (PWM_BASE + 0X10)
#define PWM2_S (PWM_BASE + 0X14)
#define PWM2_P (PWM_BASE + 0X18)
#define PWM2_CNT (PWM_BASE + 0X1C)
/*************************************************
defien RTC registers
*************************************************/
#ifdef FPGA
#define RTC_BASE 0x10002000
#else
#define RTC_BASE 0x00202000
#endif
#define RTC_YMD (RTC_BASE + 0X00) //year ,month ,day regment
#define RTC_HMS (RTC_BASE + 0X04) //hour ,minute ,second regment
#define RTC_ALRM (RTC_BASE + 0X08) //alarm time regment
#define RTC_CTRL (RTC_BASE + 0X0c) //rtc control regment
#define RTC_IEN (RTC_BASE + 0X10) //interrupt enable regment
#define RTC_ISTAT (RTC_BASE + 0X14) //interrupt status regment
#define RTC_SAMP (RTC_BASE + 0X18) //sample regment
#define RTC_WCNT (RTC_BASE + 0X1c) //watchdog count regment
#define RTC_WSVCE (RTC_BASE + 0X20) //Watchdog service regment
/*********************************************
define UART registers
*********************************************/
#ifdef FPGA
#define UART1_BASE 0X10004000
#else
#define UART1_BASE 0X00203000
#endif
#define UART1_THR (UART1_BASE+0X00)
#define UART1_RBR (UART1_BASE+0X00)
#define UART1_DLL (UART1_BASE+0X00)
#define UART1_DLH (UART1_BASE+0X04)
#define UART1_IER (UART1_BASE+0X04)
#define UART1_IIR (UART1_BASE+0X08)
#define UART1_FCR (UART1_BASE+0X08)
#define UART1_LCR (UART1_BASE+0X0c)
#define UART1_MCR (UART1_BASE+0X10)
#define UART1_LSR (UART1_BASE+0X14)
#define UART1_MSR (UART1_BASE+0X18)
#ifdef FPGA
#define UART2_BASE 0X10005000
#else
#define UART2_BASE 0X00204000
#endif
#define UART2_THR (UART2_BASE+0X00)
#define UART2_RBR (UART2_BASE+0X00)
#define UART2_DLL (UART2_BASE+0X00)
#define UART2_DLH (UART2_BASE+0X04)
#define UART2_IER (UART2_BASE+0X04)
#define UART2_IIR (UART2_BASE+0X08)
#define UART2_FCR (UART2_BASE+0X08)
#define UART2_LCR (UART2_BASE+0X0c)
#define UART2_MCR (UART2_BASE+0X10)
#define UART2_LSR (UART2_BASE+0X14)
#define UART2_MSR (UART2_BASE+0X18)
/*************************************
define LCDC registers
*************************************/
#define BASE_LCDC 0x11002000 //;BASE ADDRESS OF LCDC
#define VS_BASE 0x31200000 //;WHICH IS ASSUMED BECAUSE OF UN-ALLOCARTION
#define SSA (BASE_LCDC+0x00) //;Screen Start Address Register
#define SIZE (BASE_LCDC+0x04) //;Size Register
#define PCR (BASE_LCDC+0x08) //;Panel Configuration Register
#define HCR (BASE_LCDC+0x0c) //;Horizontal Configuration Register
#define VCR (BASE_LCDC+0x10) //;Vertical Configuration Register
#define PWMR (BASE_LCDC+0x14) //;PWM Contrast Control Register
#define LECR (BASE_LCDC+0x18) //;LCD Gray Palette Mapping Register
#define DMACR (BASE_LCDC+0x1c) //;DMA Control Register
#define LCDICR (BASE_LCDC+0x20) //;Interrupt Configuration Register
#define LCDISR (BASE_LCDC+0x24) //;Interrupt Status Register
#define LGPMR (BASE_LCDC+0x40) //;The begin of address of grey_reg
/**************************************
define SPI registers
****************************************/
#ifdef SIM
#define BASE_SPI_1 0X00205000
#define PORTF_DIR 0X0020b040
#define PORTF_DATA 0x0020b008
#define PORTF_SEL 0x0020b050
#define DMABASE 0x00221000
#endif
#ifdef FPGA
#define BASE_SPI_1 0X10006000
#define PORTF_DIR 0X1020b040
#define PORTF_DATA 0x1000b008
#define PORTF_SEL 0x1020b050
#endif
#define SPICR (BASE_SPI_1 + 0X00)
#define SPIBR (BASE_SPI_1 + 0X04)
#define SPISR (BASE_SPI_1 + 0X08)
#define SPITR (BASE_SPI_1 + 0X0C)
#define SPIRR (BASE_SPI_1 + 0x10)
#define x_location 0x94
#define y_location 0xD4
#define trigger 0x80
#define ctrlw 0x77
#define bt256 0x0007
#define spif 0x01
//
//dma
//
#define SA (DMABASE + 0X00)
#define DA (DMABASE + 0X04)
#define CTRL (DMABASE + 0X08)
#define DMAENABLE (DMABASE + 0X0C)
#define DMASTATUS (DMABASE + 0X10)
#define DACLW 0XA1040006
#define DACLR 0X91040006
/*********************************************
Define SSI Register
*********************************************/
#ifdef FPGA
#define BASE_SSI 0x10006000
#endif
#define SSI_CTRLR0 (BASE_SSI + 0x0 )
#define SSI_CTRLR1 (BASE_SSI + 0x04)
#define SSI_SSIENR (BASE_SSI + 0x08)
#define SSI_MWCR (BASE_SSI + 0x0C)
#define SSI_SER (BASE_SSI + 0x10)
#define SSI_BAUDR (BASE_SSI + 0x14)
#define SSI_TXFTLR (BASE_SSI + 0x18)
#define SSI_RXFTLR (BASE_SSI + 0x1C)
#define SSI_TXFLR (BASE_SSI + 0x20)
#define SSI_RXFLR (BASE_SSI + 0x24)
#define SSI_SR (BASE_SSI + 0x28)
#define SSI_IMR (BASE_SSI + 0x2C)
#define SSI_ISR (BASE_SSI + 0x30)
#define SSI_RISR (BASE_SSI + 0x34)
#define SSI_TXOICR (BASE_SSI + 0x38)
#define SSI_RXOICR (BASE_SSI + 0x3C)
#define SSI_RXUICR (BASE_SSI + 0x40)
#define SSI_MSTICR (BASE_SSI + 0x44)
#define SSI_ICR (BASE_SSI + 0x48)
#define SSI_DMACR (BASE_SSI + 0x4C)
#define SSI_DMATDLR (BASE_SSI + 0x50)
#define SSI_DMARDLR (BASE_SSI + 0x54)
//#define SSI_IDR (BASE_SSI + 0x58)
//#define SSI_COMP_VERSION (BASE_SSI + 0x5C)
#define SSI_DR (BASE_SSI + 0x60)
/************************************** xiaoj 03.11.20
define DMA registers
****************************************/
/*
#define DMACbase 0x11000000
#define DMACIntStatus (DMACbase+0x1020) //Read
#define DMACIntTCStatus (DMACbase+0x1050) //Read
#define DMACIntTCClear (DMACbase+0x1060) //Write
#define DMACRawIntTCStatus (DMACbase+0x1070) //Read
#define DMACIntErrorStatus (DMACbase+0x1080) //Read
#define DMACIntErrClr (DMACbase+0x1090) //Write
#define DMACRawIntErrorStatus (DMACbase+0x10a0) //Read
#define DMACEnbldChns (DMACbase+0x10B0) //Read; Indicate which channel can be used;
#define ADDRESS_CONFIGURATION (DMACbase+0x10C0)
#define DMACC0SrcAddr (DMACbase+0x1000) //DMA channel 0 registers;
#define DMACC0DestAddr (DMACbase+0x1004)
#define DMACC0Control (DMACbase+0x100c)
#define DMACC0Configuration (DMACbase+0x1010)
#define DMACC1SrcAddr (DMACbase+0x1100) //DMA channel 1 registers; R/W
#define DMACC1DestAddr (DMACbase+0x1104)
#define DMACC1Control (DMACbase+0x110c)
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