boot_gfd.s

USB 软件配置的具体工程

;/*****************************************************
;	file name :	 	boot.s
;	descrition:		boot the G4+ processor
;	history:		2006-10-17 12:59 wuer create
;*****************************************************/

	include hardware_gfd.h	
	
                           		
	AREA INT, CODE, READONLY                                                     
	ENTRY                           		; Mark first instruction to execute 

;*****************************************************************
;	vector table
;*****************************************************************
    bal		RST_DO  
	bal		EXTENT_INSTRU
	bal		SWI_DO
	bal		ABORT_PREFETCH_DO
	bal		ABORT_DATA_DO
	mov		R1,		R1				;reserved exception
	bal		IRQ_DO
	mov		r0, r0
	;bal		FIQ_DO   
	ldr		pc,=IRQ_DO
	
	




IRQ_DO      
	
	stmfd	sp!, {r0,r1}

	ldr		r0, =IRQ_R1
	str		r1, [r0]
	
	ldmfd	sp!, {r0}
	ldr		r1, =IRQ_R0
	str		r0, [r1]
	
	add		r13, r13, #4		;//restore the sp_irq top to original irq top
	
	sub		r14, r14, #4
	mov		r0, r14
	
	mrs		r1, spsr
	orr		r1, r1, #0x80
	msr		cpsr_cxsf, r1		;//change irq mode into svc
;------------------------------------------------	
	bic		r1, r1, #0x80		;//open the irq 
	
	stmfd	sp!, {r0}
	stmfd	sp!, {r14}
	stmfd	sp!, {r1}
	
	ldr		r0, =IRQ_R1
	ldr		r1, [r0]
	stmfd	sp!, {r1}
		
	ldr		r1, =IRQ_R0
	ldr		r0, [r1]
	stmfd	sp!, {r0}
	
	ldmfd	sp!, {r0,r1}
	stmfd	sp!, {r0-r12}		;//save the registers r0--r12

;-----------------------------;//search the irq vector and jump to isr
	IMPORT	int_vector_handler
	bl		int_vector_handler

;-----------------------------;//restore the register
	ldmfd	sp!, {r0-r12}
	ldmfd	sp!, {r14}
	msr		cpsr_cxsf, r14
	ldmfd	sp!, {r14}
	ldmfd	sp!, {pc}

;***********************************************************
;*	other exception handler
;***********************************************************

	
EXTENT_INSTRU                                                         
	b		EXTENT_INSTRU                                             
	                                                                  
SWI_DO    
	stmfd	sp!, {r14}
	ldmfd	sp!, {pc}^                                                    
	                                                                  
ABORT_PREFETCH_DO                                                     
	b		ABORT_PREFETCH_DO                                         
	                                                                  
ABORT_DATA_DO                                                         
	b		ABORT_DATA_DO 
                                                            
FIQ_DO                                                                
	b		FIQ_DO                                                    
                                                                      











RST_DO
	;*****************************************************************
	;	init all the stacks under all CPU mode
	;*****************************************************************	
	
	ldr		sp, =SP_SVC  		;init sp_svc
	
	mov		RTA, #0xD2			;chmod to irq and init sp_irq
	msr		cpsr_cf, RTA   
	ldr		sp, =SP_IRQ
	
	mov		RTA, #0XD1			;chomod to fiq and init sp_fiq
    msr		cpsr_cf, RTA   
    ldr		sp, =SP_FIQ  
	
	mov		RTA, #0XD7			;chomod to abt and init sp_ABT
   	msr		cpsr_cf, RTA   
    ldr		sp, =SP_ABT 
	
	mov		RTA, #0XDB			;chomod to undf and init sp_UNDF
    msr		cpsr_cf, RTA   
    ldr		sp, =SP_UND 	
    
    								;chomod to abt and init sp_sys
	mov 	RTA, #0xDF			;all interrupts disabled      
    msr		cpsr_cxsf, RTA   		;SYSTEM mode, @32-bit code mode     
    ldr		sp, =SP_SYS   	
    
    mov		RTA, #0XD3			;chmod to svc modle, CPSR IRQ bit  is disable
    msr		cpsr_c, RTA
    
;****************************************************************
; 	init the PMU and get the memory space;也可以在main（）中实现
;****************************************************************
	ldr		RTA, =0x11000000   ;配置PMU
    ldr		RTB, =0x20454551                 
    str		RTB, [ RTA ] 


	ldr		RTA, =0x11000010 	;CSE 片选参数配置
    ldr		RTB, =0x8c000005                 
    str		RTB, [ RTA ] 

	ldr		RTA, =0x11000018 	;SDRAM 参数配置1
    ldr		RTB, =0x0d105126                 
    str		RTB, [ RTA ] 
    
	ldr		RTA, =0x1100001c 	;SDRAM 参数配置2
    ldr		RTB, =0x800005a1			;？？？                 
    str		RTB, [ RTA ]
    
   
    
    
    
;****************************************************************
; 	init the EMI and get the memory space
;****************************************************************
	
    
	ldr		RTA, =0x11000000   ;CSA 片选参数配置
    ldr		RTB, =0x087D7D51                 
    str		RTB, [ RTA ]     
    
  	ldr		RTA, =0x11000004   ;CSB 片选参数配置
    ldr		RTB, =0x097D7D59                 
    str		RTB, [ RTA ]    
 
	;ldr		RTA, =0x11000018 	;SDRAM 参数配置1
    ;ldr		RTB, =0x0400800b                 
    ;str		RTB, [ RTA ] 
    
	;ldr		RTA, =0x11000018 	;SDRAM 参数配置2
    ;ldr		RTB, =0x0			;？？？                 
    ;str		RTB, [ RTA ]
    
    

               
;****************************************************
;open MMU
;****************************************************
        
    LDR     r0,=0x24000000              ; set start of Translation Table base (16k Boundary)
      
    MCR     p15, 0, r0, c2, c0, 0       ; write to CP15 register 2

;read r3

    MRC     p15, 0, r5, c3, c0, 0 
    
    ldr     r0,=0x400000f1            	; must define behaviour for domain 15 (31:30), set client,domain 2-reserved,domain 1-deny
       									; domain 0-
;write r3       									

    MCR     p15, 0, r0, c3, c0, 0       ; write to CP15 register 5

; set global core configurations 

    MRC     p15, 0, r0, c1, c0, 0       ; read CP15 register 1 into r0
    ORR     r0, r0, #(0x1 <<12)         ; enable I cache 
;    ORR     r0, r0, #(0x1 <<2)          ; enable D cache 
    ORR     r0, r0, #(0x1 <<3)          ; enable write buffer  
    ORR     r0, r0, #(0x1 <<9)          ; set R
    BIC     r0, r0, #(0x1 <<9)          ; clear S
    ORR     r0, r0, #0x1                ; enable MMU
    MCR     p15, 0, r0, c1, c0, 0       ; write cp15 register 1

    
;***************************************************************
;    	enable CPSR IRQ bit
;***************************************************************
  	mrs		RTA, cpsr
	bic		RTA, RTA, #0x80  		;set bit7 to zero
	msr		cpsr_c, RTA

;***************************************************************
;	jump to main function
;***************************************************************
	IMPORT	__main
	b		__main 
	
	
	
	
	;*************************************************************

IRQ_R1		DCD		0X0
IRQ_R0		DCD		0X0


	END