main.c

RTC设计文档

#include "hardware_reg.h"
#include "hardware.h"
#include "HA_typedef.h"
#include "stdio.h"
main()
{
	U32 i,j = 0;
	U32 sysclk;
	U32 temp;
	U32 m,n;
	U32 Time1,Time2;
	int alarm_set = 0;
	U32 addr;
	U16 data;
		
	sysclk = 60000000;	//config sysclk
	
	
	
    //****************************open all module
    
#if 0   
	*(RP)(PMU_PSCR) =0x17fff;	//open all module

	
	*(RP)(PMU_PMDR)	=0X01;		// normal
    //*(RP)(PMU_PMDR)	=0X02;
	*(RP)PMU_PLTR=0x00d200cd;	// MLTV=210,ULTV=205
	
//	for(i=0;i<100;i++);
		
	n = 2;
	m = 8*sysclk/10000000;
	*(RP)(PMU_PMCR) = (n << 8) | m;
	*(RP)(PMU_PMCR) = (1 << 12) | (n << 8) | m;
		
	*(RP)PMU_PUCR=0x1530;		//parameter PD=5,D=48
		
#endif


/*
   addr = 0;
  for (i=1;i<200;i++)
  {
     *(RP)(0x30000000+addr) = i;
     addr = addr +4;
     
  }
*/	


*(RP)EMI_SRAM_REGBASE &= 0xffffdf55;  //config the sram

*(RP)(0x24000000)=0x01;

data=*(RP)(0x24000000);



set_sysclk_60(); 
set_to_normal();
*(RP)(PMU_PSCR) =0x17fff;   //open all module
init_intc();
//init_rtc();
write_reg(0x1000200c,0x0b);        //rst_en
write_reg(0x10002024,0xaaaaaaaa);

set_ymd(2004, 12, 31);
set_hms(23, 50, 59);
set_alarm(12,31,23,51);
set_int_en(0x3f);
set_wdog_cont(0x2);
set_samp(0x400);


//for (i=0;i<200;i++);
//write_reg(0x1000200c,0xf);


//for (i=0;i<500;i++);
//write_reg(0x1000200c,0xa);



//for CODEC test
//write_reg(CLK_CTL,0x9);   //clk_divisor

/*
write_reg(CODEC_TX_FIFO,0x1);
write_reg(CODEC_TX_FIFO,0x2);
write_reg(CODEC_TX_FIFO,0x3);
write_reg(CODEC_TX_FIFO,0x4);
write_reg(CODEC_TX_FIFO,0x5);
*/
/*
write_reg(CODEC_TX_FIFO,0x6);
write_reg(CODEC_TX_FIFO,0x7);
write_reg(CODEC_TX_FIFO,0x8);
write_reg(CODEC_TX_FIFO,0x9);
write_reg(CODEC_TX_FIFO,0xa);
write_reg(CODEC_TX_FIFO,0xb);
write_reg(CODEC_TX_FIFO,0xc);
write_reg(CODEC_TX_FIFO,0xd);
write_reg(CODEC_TX_FIFO,0xe);
write_reg(CODEC_TX_FIFO,0xf);
write_reg(CODEC_TX_FIFO,0x10);
*/
//write_reg(CODEC_CTL,0x1);

//write_reg(VOL_CTL,0x3ff);

//config the DMA  for TX
  
//write_reg(0x11001000,0x30000000);
//write_reg(0x11001004,CODEC_TX_FIFO);
//write_reg(0x1100100c,0x4d4ad);
//write_reg(0x11001010,0x2003);


//write_reg(CODEC_CTL,0x1);  //enable the codec
//config the DMA  for RX
/*  
write_reg(0x11001000,CODEC_RX_FIFO);
write_reg(0x11001004,0x20000000);
write_reg(0x1100100c,0x14ad);
write_reg(0x11001010,0x245);
*/

while(1);

}