📄 smc_apb_if.v
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begin
out_F <= in_Pwdata[31:16];
out_D <= in_Pwdata[3:0];
end
`CharacterTransferTime_r:
begin
out_WI <= in_Pwdata[15:8];
out_N <= in_Pwdata[7:0];
end
`BlockTransferTime_r:
begin
out_BGT <= in_Pwdata[15:8];
out_BWI <= in_Pwdata[7:4];
out_CWI <= in_Pwdata[3:0];
end
`BlockTransferLength:
begin
out_BlockLength <= in_Pwdata[7:0];
end
`FIFOControl:
begin
txFIFO_write_r <= in_Pwdata[0];
rxFIFO_read_r <= in_Pwdata[1];
end
`TransmitFIFOData:
begin
out_tx_data <= in_Pwdata[7:0];
end
endcase
end
end
wire out_ColdEnable_trig;
always @(posedge in_Pclk or negedge rst_preset_n_a)
begin
if(!rst_preset_n_a)
ColdEnable_q <= 1'b0;
else
ColdEnable_q <= ColdEnable_r;
end
assign out_ColdEnable_trig = ColdEnable_r & ~ColdEnable_q;
always @(posedge in_Pclk or negedge rst_preset_n_a)
begin
if(!rst_preset_n_a)
begin
cnt <= 7'b1111111; //keep sevaral periods
out_ColdEnable <= 1'b0;
end
else
begin
if (out_ColdEnable_trig == 1'b1)
out_ColdEnable <= 1'b1;
if ( out_ColdEnable == 1'b1)
cnt <= cnt - 1'b1;
if (cnt == 7'b0)
begin
out_ColdEnable <= 1'b0;
cnt <= 7'b1111111;
end
end
end
wire out_WarmEnable_trig;
always @(posedge in_Pclk or negedge rst_preset_n_a)
begin
if(!rst_preset_n_a)
WarmEnable_q <= 1'b0;
else
WarmEnable_q <= WarmEnable_r;
end
assign out_WarmEnable_trig = WarmEnable_r & ~WarmEnable_q;
always @(posedge in_Pclk or negedge rst_preset_n_a)
begin
if(!rst_preset_n_a)
begin
cnt1 <= 7'b1111111; //keep sevaral periods
out_WarmEnable <= 1'b0;
end
else
begin
if (out_WarmEnable_trig == 1'b1)
out_WarmEnable <= 1'b1;
if ( out_WarmEnable == 1'b1)
cnt1 <= cnt1 - 1'b1;
if (cnt1 == 7'b0)
begin
out_WarmEnable <= 1'b0;
cnt1 <= 7'b1111111;
end
end
end
//indicate
wire out_indicate_trig;
always @(posedge in_Pclk or negedge rst_preset_n_a)
begin
if(!rst_preset_n_a)
out_indicate_q <= 2'b00;
else
out_indicate_q <= out_indicate_r;
end
assign out_indicate_trig = (out_indicate_r[0] & ~out_indicate_q[0]) | (out_indicate_r[1] & ~out_indicate_q[1]);
always @(posedge in_Pclk or negedge rst_preset_n_a)
begin
if(!rst_preset_n_a)
begin
cnt_indi <= 8'b11111111;
out_indicate <= 2'b00;
end
else
begin
if (out_indicate_trig == 1'b1)
begin
out_indicate <= out_indicate_r;
end
if (out_indicate != 2'b0)
cnt_indi <= cnt_indi -1'b1;
if (cnt_indi == 8'b0)
begin
out_indicate <= 2'b00;
cnt_indi <= 8'b11111111;
end
end
end
//out_txFIFO_write
always @(posedge in_Pclk or negedge rst_preset_n_a)
begin
if(!rst_preset_n_a)
txFIFO_write_q <= 1'b0;
else
txFIFO_write_q <= txFIFO_write_r;
end
assign out_txFIFO_write = txFIFO_write_r & ~txFIFO_write_q;
//out_rxFIFO_read
always @(posedge in_Pclk or negedge rst_preset_n_a)
begin
if(!rst_preset_n_a)
rxFIFO_read_q <= 1'b0;
else
rxFIFO_read_q <= rxFIFO_read_r;
end
assign out_rxFIFO_read = rxFIFO_read_r & ~rxFIFO_read_q;
//===============================================
//output logic
//===============================================
assign ctrl = {8'b0,Div,9'b0,out_indicate_r,out_StateOfCard,out_T,out_TS,WarmEnable_r,ColdEnable_r};
assign etu = {out_F,12'b0,out_D};
assign int_en = {25'b0,out_parity_en,out_timeout_reset_en,out_timeout_character_en,out_timeout_block_en,out_empty_en,out_overrun_en,out_dataValid_en};
assign int_status ={25'b0,in_parity_status,in_timeout_reset_status,in_timeout_character_status,in_timeout_block_status,in_empty_status,in_OverrunError_status,in_dataValid_status};
assign character_time = {16'b0,out_WI,out_N};
assign block_time = {16'b0,out_BGT,out_BWI,out_CWI};
assign rx_FIFO_data = {24'b0 , in_rx_data};
assign tx_FIFO_data = {24'b0 , out_tx_data};
assign blocklength = {24'b0,out_BlockLength};
always @ (in_Psel or
in_Penable or
in_Pwrite or
in_Paddr or
ctrl or
int_en or
int_status or
etu or
character_time or
block_time or
blocklength or
rx_FIFO_data or
tx_FIFO_data
)
begin
if((in_Psel==1) && (in_Penable==1) && (in_Pwrite==0))
begin
case(in_Paddr)
`Control_r : out_Prdata = ctrl;
`InterruptEnable_r : out_Prdata = int_en;
`InterruptStatus_r : out_Prdata = int_status;
`BasicTimeUnit_r : out_Prdata = etu;
`CharacterTransferTime_r : out_Prdata = character_time;
`BlockTransferTime_r : out_Prdata = block_time;
`BlockTransferLength : out_Prdata = blocklength;
`ReceiverFIFOData : out_Prdata = rx_FIFO_data;
`TransmitFIFOData : out_Prdata = tx_FIFO_data;
default : out_Prdata = 32'h00000000;
endcase
end
else
out_Prdata = 32'h00000000;
end
always @(posedge in_Pclk or negedge rst_preset_n_a)
begin
if(!rst_preset_n_a)
out_ReadStatusRegister <= 1'b0;
else
if((in_Psel==1) && (in_Penable==1) && (in_Pwrite==0)&&(in_Paddr==`InterruptStatus_r))
out_ReadStatusRegister <= 1'b1;
end
endmodule
/* 寄存一拍
always @(posedge in_Pclk or negedge rst_preset_n_a)
begin
if(rst_preset_n_a==0)
in_intstatus_r <= `AC97INT_WIDTH'b0;
else
in_intstatus_r <= in_intstatus;
end
//=====================================
//generate codec read data
//=====================================
always @ (posedge in_Pclk or negedge rst_preset_n_a)
begin
if(rst_preset_n_a==0)
codec_read_data <= `CODECDATA_WIDTH'b0;
else
if(!out_codec_cmd)
codec_read_data <= out_codec_data;
else
codec_read_data <= sync_codec_data_in;
end
//synchronize in_codec_data signal
always @ (posedge in_Pclk or negedge rst_preset_n_a)
begin
if(rst_preset_n_a==0)
sync_codec_data_tmp <= `CODECDATA_WIDTH'b0;
else
sync_codec_data_tmp <= in_codec_data;
end
always @ (posedge in_Pclk or negedge rst_preset_n_a)
begin
if(rst_preset_n_a==0)
sync_codec_data_in <= `CODECDATA_WIDTH'b0;
else
sync_codec_data_in <= sync_codec_data_tmp;
end
//=======================================
//generate control register write pulse
//=======================================
always @ (posedge in_Pclk or negedge rst_preset_n_a)
begin
if(rst_preset_n_a==0)
out_conrwrite <= 1'b0;
else
if(in_Psel && in_Penable && in_Pwrite && (in_Paddr == `CONR))
out_conrwrite <= 1'b1;
else
out_conrwrite <= 1'b0;
end
//assign out_conrwrite = in_Psel && in_Penable && in_Pwrite && (in_Paddr == `CONR);
//=======================================
//generate crac register write pulse
//=======================================
always @ (posedge in_Pclk or negedge rst_preset_n_a)
begin
if(rst_preset_n_a==0)
out_cracwrite <= 1'b0;
else
if(in_Psel && in_Penable && in_Pwrite && (in_Paddr == `CRAC))
out_cracwrite <= 1'b1;
else
out_cracwrite <= 1'b0;
end
*/
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