receiver_fifo.v

自己设计的Smartcard功能模块

//******************************************************************
//   (C) COPYRIGHT  2007  Southeast University ASIC Center
//    ALL RIGHTS RESERVED
//    File     : receiver_FIFO.v
//    Author   : Jun Yi 
//    Data     : 2007-9-20
//    Version  : 1.0
//    Abstract : receiver_FIFO
//*******************************************************************
module receiver_FIFO(
        // clock and reset
                   in_Pclk          ,
                   clk_div          ,
                   rst_preset_n_a   ,
        // fifo control signal
                   in_ReceiverWe    ,
                   in_read          ,
                   out_FullIndicator,
             //      out_EmptyIndicator    ,     
                   out_AmostFull    ,
                                   out_DataValid,
        // fifo data           
                   in_rxData        ,
                   out_rxData       );
  //default fifo parameter :
  // 32 bit width
  // 8 level 
  // fifo pointer width is 4 bit                
        
                   
        // clock and reset
  input                         clk_div          ; 
  input                         in_Pclk          ;                
  input                         rst_preset_n_a   ;                 

        // fifo control signal
  input                         in_ReceiverWe    ;// write fifo enable                 
  input                         in_read        ;// read fifo enable
  output                        out_AmostFull  ;// fifo almost full ,assert when fifo has last 1 level to
                                                 // be full
//  output                        out_EmptyIndicator  ;// fifo empty indication
  output                        out_FullIndicator   ;// fifo full indication
  output                        out_DataValid;
  
        // fifo data           
  output[`FIFOWIDTH-1:0]         out_rxData   ;// fifo read data output
  input [`FIFOWIDTH-1:0]         in_rxData    ;// fifo write data input                 
  
  reg   [`FIFOPTWIDTH-1:0]      rpointer          ;// fifo read pointer,point to data to be read out
  reg   [`FIFOPTWIDTH-1:0]      wpointer          ;// fifo write pointer ,point to data to be write in
  reg   [`FIFOWIDTH-1:0]        fifo_mem[`FIFODEPTH-1:0];// fifo register array
  wire  [`FIFOPTWIDTH-2:0]      fifo_depth        ;// fifo depth,means the number of data in the fifo  
 
  wire out_EmptyIndicator;
///***********************************************************************  
//// full ,empty , halfempty generating    ///////////////////////////////
//// overflow ,underflow  generating       ///////////////////////////////
///***********************************************************************
  // if read pointer is equal to write pointer and fifo depth is 0, fifo empty
  assign out_EmptyIndicator = (fifo_depth == 0) & (rpointer[`FIFOPTWIDTH-1]
                                    ==wpointer[`FIFOPTWIDTH-1]);
  
  // if read pointer is not equal to write pointer and fifo depth is 0, fifo full
  assign out_FullIndicator = (fifo_depth == 0) & (rpointer[`FIFOPTWIDTH-1] 
                                     !=wpointer[`FIFOPTWIDTH-1]);  
  // fifo depth is write pointer minus read pointer,this is a carry borrow subtration
  assign fifo_depth = wpointer[`FIFOPTWIDTH-2:0] - rpointer[`FIFOPTWIDTH-2:0];
  // if fifo depth is n'b11..111 , it means fifo has last 1 level to be full
  assign out_AmostFull = &fifo_depth; // 1 data to full
  assign out_rxData = fifo_mem[rpointer[`FIFOPTWIDTH-2:0]];

/////////////added for data_valid sent to STATUS_REGISTER
  assign out_DataValid = fifo_depth != 1'b0;
  
////////////
  
///*************************************************************************
///  write data ,wpointer  /////////////////////////////////////////////////
///*************************************************************************
  integer i; // index
// if  write fifo enable and fifo is not full,push the data into where 
// the write pointer point to. And then write pointer increase by 1. 
  always @ (posedge clk_div or negedge rst_preset_n_a)
    if(~rst_preset_n_a)
      for(i=0;i<`FIFODEPTH;i=i+1)
        fifo_mem[i] <= 0;
    else //if(~rst_preset_n_a) 
      if( in_ReceiverWe &(!out_FullIndicator))
        fifo_mem[wpointer[`FIFOPTWIDTH-2:0]] <= in_rxData;
          
  always @ (posedge clk_div or negedge rst_preset_n_a)
    if(~rst_preset_n_a)
      wpointer <= 0;
    else//if(~rst_preset_n_a)
      if(in_ReceiverWe & (!out_FullIndicator))
        wpointer <= wpointer + 1;        
               
////********************************************************************
///// read data , rpointer /////////////////////////////////////////////
////********************************************************************

// fifo output data is always connected to the data read pointer point to.  
// if read fifo enable and fifo is not empty, read pointer increase by 1. 
  always @ (posedge in_Pclk or negedge rst_preset_n_a)
    if(~rst_preset_n_a)
      rpointer <= 0;
    else //if(~rst_preset_n_a)
      if( in_read &(!out_EmptyIndicator))
          rpointer <= rpointer + 1;
  
endmodule