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serial_out <= 1'b0;
end
`CHARACTER_TRANSMITTER_DATA:
begin
direction <= 1'b0;
if (count5_eq_0)
count5 <= COUNT - 1'b1;
else
begin
if(count5 == 5'h1)
begin
if (bit_counter_r > 3'b0)
begin
bit_counter_r <= bit_counter_r - 1'b1;
{bit_out_r,shift_out_r[6:1]} <= {shift_out_r[6],shift_out_r[5:0]};
current_state <= `CHARACTER_TRANSMITTER_DATA;
end
else // end of byte
begin
bit_out_r <= parity_xor_r;
current_state <= `CHARACTER_TRANSMITTER_PARITY;
end
count5 <= 5'h0;
end
else
count5 <= count5 - 1'b1;
end
serial_out <= bit_out_r; // set output pin
end
`CHARACTER_TRANSMITTER_PARITY:
begin
direction <= 1'b0;
if (count5_eq_0)
count5 <= COUNT - 1'b1;
else
if (count5 == 5'h1)
begin
count5 <= 5'b0;
current_state <= `CHARACTER_TRANSMITTER_GUARDTIME;
end
else
count5 <= count5 - 1'b1;
serial_out <= bit_out_r;
end
`CHARACTER_TRANSMITTER_GUARDTIME:
begin
direction <= 1'b0;
if (N == 8'b11111111)
current_state <= `IDLE;
else
begin
if (count5_eq_0)
count5 <= COUNT - 1'b1;
else
begin
if(count5 == 5'h1)
begin
if (N > 8'b1)
begin
N <= N - 1'b1;
current_state <= `CHARACTER_TRANSMITTER_GUARDTIME;
end
else
begin
current_state <= `IDLE;
end
count5 <= 5'h0;
end
else
count5 <= count5 - 1'b1;
end
serial_out <= 1'b1;
end
end
//////////////////////////////////////////////////////////////////////
// BLOCK_RECEIVER BLOCK_RECEIVER BLOCK_RECEIVER BLOCK_RECEIVER
//////////////////////////////////////////////////////////////////////
`BLOCK_RECEIVER_GET_CWT_BWT:
begin
count7 <= BWT_counter;
count8 <= CWT_counter;
current_state <= `BLOCK_RECEIVER_WAIT_START;
end
`BLOCK_RECEIVER_WAIT_START: //BWT overtime check
begin
if (count7 == 14'b0)
begin
out_BWT_OvertimeIndicate_r<= 1'b1;
if(in_readStatusRegister)
begin
current_state <= `IDLE;
out_BWT_OvertimeIndicate_r<= 1'b0;
end
end
else
begin
direction <= 1'b1;
B_C_sent <= 1'b0;
if (serial_in==1'b0)
begin
count5 <= COUNT -1'b1;
current_state <= `BLOCK_RECEIVER_REC_START;
count7 <= BWT_counter;
end
else
begin
count5 <= count5 -1'b1;
if (count5_eq_0)
begin
count7 <= count7 - 1'b1;
count5 <= COUNT - 1'b1;
end
current_state <= `BLOCK_RECEIVER_WAIT_START;
end
end
end
`BLOCK_RECEIVER_WAIT_START1: //CWT overtime check
begin
if (count8 == 6'b0)
begin
out_CWT_OvertimeIndicate_r<= 1'b1;
if(in_readStatusRegister)
begin
out_CWT_OvertimeIndicate_r<= 1'b0;
current_state <= `IDLE;
end
end
else
begin
direction <= 1'b1;
B_C_sent <= 1'b1;
if (serial_in==1'b0)
begin
count5 <= COUNT -1'b1;
current_state <= `BLOCK_RECEIVER_REC_START;
count8 <= CWT_counter;
end
else
begin
count5 <= count5 -1'b1;
if (count5_eq_0)
begin
count8 <= count8 - 1'b1;
count5 <= COUNT - 1'b1;
end
current_state <= `BLOCK_RECEIVER_WAIT_START1; end
end
end
`BLOCK_RECEIVER_REC_START:
begin
direction <= 1'b1;
if (count5_eq_halfcount5)
begin
if (serial_in==1'b1) // no start bit
begin
case(B_C_sent == 1'b0)
0:current_state <= `BLOCK_RECEIVER_WAIT_START;
1:current_state <= `BLOCK_RECEIVER_WAIT_START1;
endcase
count5 <= COUNT -1'b1;
end
else // start bit detected
current_state <= `BLOCK_RECEIVER_REC_PREPARE;
end
count5 <= count5 - 1'b1;
end
`BLOCK_RECEIVER_REC_PREPARE:
begin
direction <= 1'b1;
count5 <= count5 - 1'b1;
rbit_counter_r <= 3'b111; //8 bits in a word
if (count5_eq_0)
begin
current_state <= `BLOCK_RECEIVER_REC_BIT;
count5 <= COUNT -1'b1;
rshift_r <= 8'b0;
end
end
`BLOCK_RECEIVER_REC_BIT:
begin
direction <= 1'b1;
count5 <= count5 - 1'b1;
if (count5_eq_0)
begin
current_state <= `BLOCK_RECEIVER_END_BIT;
end
else
if (count5_eq_halfcount5) // read the bit
rshift_r[7:0] <= { rshift_r[6:0],serial_in}; //suppose the LSB arrive first
end
`BLOCK_RECEIVER_END_BIT:
begin
direction <= 1'b1;
if (rbit_counter_r==3'b0) // no more bits in word
begin
if (BlockLength ==2'h0)
current_state <= `IDLE;
else
current_state <= `BLOCK_RECEIVER_WAIT_START1;
end
else
begin
current_state <= `BLOCK_RECEIVER_REC_BIT;
rbit_counter_r <= rbit_counter_r - 1'b1;
end
count5 <= COUNT -2'b10;
end
////////////////////////////////////////////////////////////////
// BLOCK_TRANSMITTER BLOCK_TRANSMITTER BLOCK_TRANSMITTER
////////////////////////////////////////////////////////////////
`BLOCK_TRANSMITTER_PREPARE:
begin
direction <= 1'b0;
if (in_TransmitFIFOEmpty)
begin
current_state <= `IDLE;
serial_out <= 1'b1;
end
else
begin
out_TransmitRead_r <= 1'b0;
serial_out <= 1'b1;
N <= in_N;
current_state <= `BLOCK_TRANSMITTER_TRANSMITTED;
end
end
`BLOCK_TRANSMITTER_TRANSMITTED :
begin
direction <= 1'b0;
serial_out <= 1'b1;
out_TransmitRead_r <= 1'b1;
bit_counter_r <= 3'b111;
count5 <= COUNT -1'b1;
if (TS == 1'b0)
{bit_out_r,shift_out_r[6:0]} <= in_txDataFromTxFIFO;
else
if (TS == 1'b1)
{bit_out_r,shift_out_r[6:0]} <= ~(in_txDataFromTxFIFO);
current_state <= `BLOCK_TRANSMITTER_START;
end
`BLOCK_TRANSMITTER_START:
begin
direction <= 1'b0;
out_TransmitRead_r <= 1'b0;
if (count5_eq_0)
begin
count5 <= COUNT - 1'b1;
current_state <= `BLOCK_TRANSMITTER_DATA;
end
else
begin
if (count5 == 5'h1)
begin
count5 <= 5'h0;
end
else
count5 <= count5 - 1'b1;
end
serial_out <= 1'b0;
end
`BLOCK_TRANSMITTER_DATA:
begin
direction <= 1'b0;
if (count5_eq_0)
count5 <= COUNT - 1'b1;
else
begin
if(count5 == 5'h1)
begin
if (bit_counter_r > 3'b0)
begin
bit_counter_r <= bit_counter_r - 1'b1;
{bit_out_r,shift_out_r[6:1]} <= {shift_out_r[6],shift_out_r[5:0]};
current_state <= `BLOCK_TRANSMITTER_DATA;
end
else // end of byte
begin
//BlockLength <= BlockLength -1'b1;
current_state <= `BLOCK_TRANSMITTER_GUARDTIME;
end
count5 <= 5'h0;
end
else
count5 <= count5 - 1'b1;
end
serial_out <= bit_out_r; // set output pin
end
`BLOCK_TRANSMITTER_GUARDTIME:
begin
direction <= 1'b0;
shift_out_r <= 7'b0;
if (N == 8'b11111111)
current_state <= `IDLE;
else
begin
if (count5_eq_0)
begin
count5 <= COUNT - 1'b1;
// current_state <= BLOCK_TRANSMITTER_GUARDTIME;
end
else
begin
if(count5 == 5'h1)
begin
if (N > 8'b1)
begin
N <= N - 1'b1;
current_state <= `BLOCK_TRANSMITTER_GUARDTIME;
end
else
begin
if (BlockLength == 1'b1)
current_state <= `BLOCK_TRANSMITTER_BGT;
else
current_state <= `BLOCK_TRANSMITTER_PREPARE;
BlockLength <= BlockLength -1'b1;
end
count5 <= 5'h0;
end
else
count5 <= count5 - 1'b1;
end
serial_out <= 1'b1;
end
end
`BLOCK_TRANSMITTER_BGT:
begin
direction <= 1'b0;
BlockLength <= 1'b0;
if (count5_eq_0)
count5 <= COUNT - 1'b1;
else
begin
if(count5 == 5'h1)
begin
if (BGT == 8'b1)
begin
current_state <= `IDLE;
end
else
begin
BGT <= BGT - 1'b1;
current_state <= `BLOCK_TRANSMITTER_BGT;
end
count5 <= 5'h0;
end
else
count5 <= count5 - 1'b1;
end
serial_out <= 1'b1;
end
default: current_state <= `IDLE;
endcase
end //end else
end //end always
//when the rf_push_r have a pesedge from '0' to '1', give a out_ReceiverWe.
always @(posedge clk_div or negedge rst_preset_n_a)
begin
if(!rst_preset_n_a)
rf_push_q_r <= 0;
else
rf_push_q_r <= rf_push_r;
end
assign out_ReceiverWe = rf_push_r & ~rf_push_q_r;
always @(posedge clk_div or negedge rst_preset_n_a)
begin
if(!rst_preset_n_a)
begin
out_OverrunErrorIndicator_r <= 1'b0;
end
else
begin
if(in_rFIFOFull & out_ReceiverWe)
out_OverrunErrorIndicator_r <= 1'b1;
else
if(in_readStatusRegister)
out_OverrunErrorIndicator_r <= 1'b0;
end
end
always @(posedge clk_div or negedge rst_preset_n_a)
begin
if(!rst_preset_n_a)
begin
out_TransmitterEmptyIndictor <= 1'b0;
end
else
begin
if (in_TransmitFIFOEmpty & (current_state==`IDLE))
out_TransmitterEmptyIndictor <= 1'b1 ;
else
if(in_readStatusRegister)
out_TransmitterEmptyIndictor <= 1'b0;
end
end
endmodule
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