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direction <= 1'b1;
B_C_sent <= 1'b0;
if (serial_in==1'b0)
begin
current_state <= `RESET_REC_START;
count2 <= 16'b1001110000111111;
end
else
begin
count2 <= count2 - 1'b1;
current_state <= `RESET_WAIT_ATR;
end
end
end
////////
`RESET_WAIT_ATR1:
begin
if (count4 == 'h0)
begin
out_ATR_exceed9600ETUIndicator_r <= 1'b1; //overtime register,check whether the card can provide any response
current_state <= `IDLE;
if(in_readStatusRegister)
begin
out_ATR_overtimeIndicator_r <= 1'b0;
// current_state <= `IDLE;
end
end
else
begin
direction <= 1'b1;
B_C_sent <= 1'b1;
count3 <= DEFAULT_ETU -1'b1;
if (serial_in==1'b0)
begin
current_state <= `RESET_REC_START;
count4 <= COUNT4;
end
else
begin
count4 <= count4 - 1'b1;
current_state <= `RESET_WAIT_ATR1;
end
end
end
////////
`RESET_REC_START:
begin
direction <= 1'b1;
if (count3_eq_halfcount3) // check the pulse
begin
if (serial_in==1'b1)
begin // no start bit
case(B_C_sent == 1'b0)
1'b0:current_state <= `RESET_WAIT_ATR;
1'b1:current_state <= `RESET_WAIT_ATR1;
endcase
current_state <= `RESET_WAIT_ATR;
end
else
current_state <= `RESET_REC_PREPARE;
end
count3 <= count3 - 1'b1;
end
`RESET_REC_PREPARE:
begin
count3 <= count3 - 1'b1;
direction <= 1'b1;
rbit_counter_r <= 3'b111; //8 bits in a word
if (count3 == 1'b0)
begin
count3 <= DEFAULT_ETU -1'b1;
current_state <= `RESET_REC_BIT;
// count3 <= DEFAULT_ETU -1'b1;
rshift_r <= 8'b0;
end
end
`RESET_REC_BIT:
begin
direction <= 1'b1;
if (count3_eq_0)
begin
current_state <= `RESET_END_BIT;
count3 <= DEFAULT_ETU - 1'b1;
end
if (count3_eq_halfcount3) // read the bit
rshift_r[7:0] <= {rshift_r[6:0],serial_in }; //default input is from the LSB
count3 <= count3 - 1'b1;
end
`RESET_END_BIT: //attention to character_number
begin
direction <= 1'b1;
if (rbit_counter_r==3'b0) // no more bits in word
current_state <= `RESET_REC_PARITY;
else // else we have more bits to read
begin
current_state <= `RESET_REC_BIT;
rbit_counter_r <= rbit_counter_r - 1'b1;
end
count3 <= DEFAULT_ETU -2'b10;
end
`RESET_REC_PARITY:
begin
direction <= 1'b1;
if (count3_eq_0)
begin
current_state <= `RESET_CA_LC_PARIT;
count3 <= DEFAULT_ETU -1'b1;
end
else
if (count3_eq_halfcount3) // read the parity
begin
rparity_r <= serial_in;
end
count3 <= count3 - 1'b1;
end
`RESET_CA_LC_PARIT:
begin
direction <= 1'b1;
rparity_xor_r <= ^{rshift_r,rparity_r};
current_state <= `RESET_CHECK_PARITY;
count3 <= DEFAULT_ETU -2'b10;
end
`RESET_CHECK_PARITY:
begin
direction <= 1'b1;
out_ParityErrorIndicator_r <= (rparity_xor_r == 1); // indicate error if rparity_xor_r == 1
current_state <= `RESET_INDICATE_ERROE;
count3 <= count3 - 1'b1;
end
`RESET_INDICATE_ERROE:
begin
if (count3_eq_halfcount3) //10.5 send out the result in the WAIT1
begin
direction <= 1'b0;
case (out_ParityErrorIndicator_r)
0:serial_out <= 1'b1;
1:serial_out <= 1'b0;
endcase
count3 <= DEFAULT_ETU -1'b1;
current_state <= `RESET_WAIT1;
end
else
direction <= 1'b1;
count3 <= count3 - 1'b1;
end
`RESET_WAIT1:
begin
direction <= 1'b0;
if (count3_eq_0)
begin
count3 <= DEFAULT_ETU -1'b1;
current_state <= `RESET_HOLD1;
end
else
begin
serial_out <= serial_out; //keep one ETU
if (serial_out == 1'b0)
begin
rshift_r <= 8'b0;
character_number <= character_number;
end
else
begin
character_number <= character_number-1'b1;
out_rxDataToFIFO_r <= rshift_r;
rf_push_r <= 1'b1;
end
end
count3 <= count3 - 1'b1;
end
`RESET_HOLD1:
begin
direction <= 1'b0;
if (count3_eq_halfcount3)
begin
if (character_number == 5'b0)
current_state <= `IDLE;
else
current_state <= `RESET_WAIT_ATR1;
serial_out <=1'b1;
end
count3 <= count3 - 1'b1;
end
`CHARACTER_RECEIVER_WAIT_START: //960*D*WI*ETU
begin
if (count6 == 25'b0)
begin
out_character_OvertimeIndicate_r<= 1'b1;
if(in_readStatusRegister)
begin
current_state <= `IDLE;
out_character_OvertimeIndicate_r<= 1'b0;
end
end
else
begin
direction <= 1'b1;
if (serial_in==1'b0)
begin
count5 <= COUNT -1'b1;
current_state <= `CHARACTER_RECEIVER_REC_START;
count6 <= character_transfer_overtime_r; //count6 is the overtime register
end
else
begin
count5 <= count5 -1'b1;
if (count5_eq_0)
begin
count6 <= count6 - 1'b1;
count5 <= COUNT - 1'b1;
end
current_state <= `CHARACTER_RECEIVER_WAIT_START;
end
end
end
`CHARACTER_RECEIVER_REC_START:
begin
direction <= 1'b1;
if (count5_eq_halfcount5)
begin
if (serial_in == 1'b1) // no start bit
current_state <= `CHARACTER_RECEIVER_WAIT_START;
else // start bit detected
current_state <= `CHARACTER_RECEIVER_REC_PREPARE;
end
count5 <= count5 - 1'b1;
end
`CHARACTER_RECEIVER_REC_PREPARE:
begin
direction <= 1'b1;
count5 <= count5 - 1'b1;
rbit_counter_r <= 3'b111; //8 bits in a word
if (count5_eq_0)
begin
current_state <= `CHARACTER_RECEIVER_REC_BIT;
count5 <= COUNT -1'b1;
rshift_r <= 8'b0;
end
end
`CHARACTER_RECEIVER_REC_BIT:
begin
direction <= 1'b1;
if (count5_eq_0)
begin
current_state <= `CHARACTER_RECEIVER_END_BIT;
end
else
if (count5_eq_halfcount5) // read the bit
rshift_r[7:0] <= {rshift_r[6:0],serial_in}; //suppose the LSB arrive first
count5 <= count5 - 1'b1;
end
`CHARACTER_RECEIVER_END_BIT:
begin
direction <= 1'b1;
if (rbit_counter_r==3'b0) // no more bits in word
current_state <= `CHARACTER_RECEIVER_REC_PARITY;
else
begin
current_state <= `CHARACTER_RECEIVER_REC_BIT;
rbit_counter_r <= rbit_counter_r - 1'b1;
end
count5 <= COUNT -2'b10;
end
`CHARACTER_RECEIVER_REC_PARITY:
begin
direction <= 1'b1;
if (count5_eq_0)
begin
count5 <= COUNT - 1'b1;
current_state <= `CHARACTER_RECEIVER_CA_LC_PARITY;
end
else
if (count5_eq_halfcount5) // read the parity
rparity_r <= serial_in;
count5 <= count5 - 1'b1;
end
`CHARACTER_RECEIVER_CA_LC_PARITY:
begin
direction <= 1'b1;
rparity_xor_r <= ^{rshift_r,rparity_r}; // calculate parity on all incoming data
current_state <= `CHARACTER_RECEIVER_CHECK_PARITY;
count5 <= COUNT - 2'b10;
end
`CHARACTER_RECEIVER_CHECK_PARITY:
begin
direction <= 1'b1;
out_ParityErrorIndicator_r <= rparity_xor_r == 1; // indicate error if rparity_xor_r == 1
current_state <= `CHARACTER_RECEIVER_INDICATE_ERROR;
count5 <= count5 - 1'b1;
end
`CHARACTER_RECEIVER_INDICATE_ERROR:
begin
count5 <= count5 - 1'b1;
if (count5_eq_halfcount5) //10.5 send out the result in the WAIT1
begin
direction <= 1'b0;
case (out_ParityErrorIndicator_r)
0:serial_out <= 1'b1;
1:serial_out <= 1'b0;
endcase
count5 <= COUNT -1'b1;
current_state <= `CHARACTER_RECEIVER_WAIT1;
end
end
`CHARACTER_RECEIVER_WAIT1:
begin
count5 <= count5 - 1'b1;
direction <= 1'b0;
if (count5_eq_0)
begin
count5 <= COUNT -1'b1;
current_state <= `CHARACTER_RECEIVER_HOLD;
end
else
begin
serial_out <= serial_out; //keep one ETU
if (serial_out == 1'b0)
begin
rshift_r <= 8'b0;
end
else
begin
if (TS == 1'b0) //3B
out_rxDataToFIFO_r <= rshift_r;
else
if(TS == 1'b1) //3F
out_rxDataToFIFO_r <= ~rshift_r;
rf_push_r <= 1'b1;
end
end
end
`CHARACTER_RECEIVER_HOLD:
begin
serial_out <=1'b1;
direction <= 1'b0;
if (count5_eq_halfcount5)
current_state <= `IDLE;
else
current_state <= `CHARACTER_RECEIVER_HOLD;
count5 <= count5 - 1'b1;
end
`CHARACTER_TRANSMITTER_PREPARE:
begin
direction <= 1'b0;
if (in_TransmitFIFOEmpty)
begin
current_state <= `IDLE;
serial_out <= 1'b1;
end
else
begin
if (count10 == 2'b0)
begin
serial_out <= 1'b1;
current_state <= `CHARACTER_TRANSMITTER_TRANSMITTED;
end
if (count10 == 3'b001)
begin
out_TransmitRead_r <= 1'b1;
parity_xor_r <= ^in_txDataFromTxFIFO[7:0];
if (TS == 1'b0) //3B
{ bit_out_r,shift_out_r[6:0]} <= in_txDataFromTxFIFO;
else
if (TS == 1'b1) //3F
{bit_out_r,shift_out_r[6:0]} <= ~(in_txDataFromTxFIFO);
end
else
out_TransmitRead_r <= 1'b0;
end
count10 <= count10 - 1'b1;
end
`CHARACTER_TRANSMITTER_TRANSMITTED :
begin
bit_counter_r <= 3'b111;
count5 <= COUNT -1'b1;
current_state <= `CHARACTER_TRANSMITTER_START;
end
`CHARACTER_TRANSMITTER_START:
begin
direction <= 1'b0;
if (count5_eq_0)
count5 <= COUNT - 1'b1;
else
begin
if (count5 == 5'h1)
begin
count5 <= 5'h0;
current_state <= `CHARACTER_TRANSMITTER_DATA;
end
else
count5 <= count5 - 1'b1;
end
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