smartcard.v

自己设计的Smartcard功能模块

//******************************************************************
//   (C) COPYRIGHT  2007  Southeast University ASIC Center
//    ALL RIGHTS RESERVED
//    File     : SmartCard.v
//    Author   : Jun Yi 
//    Data     : 2007-9-20
//    Version  : 1.0
//    Abstract : State Machine of the whole system：RESET STATE ,CHARACTER TRANSFER, BLOCK TRANSFER
//*******************************************************************

module Smartcard(
                 clk_div,
                 rst_preset_n_a,
                                 
                 //input output signal at the IO line                            
                 serial_in,
                 serial_out,
                 Reset,
                 direction,
                                                         
                 //control signal
                 indicate,                               
                 TS,
                 StateOfCard,
                 ColdEnable,
                 WarmEnable,
                 T,
                                 
                                 //for ETU time  set signal  
                 F,
                 D,
                                 //for character overtime and guardtime
                 in_N,
                 WI,                       
                                         
                 //for block overtime and guardtime
                 in_BWI,
                 in_CWI,
                 in_BGT,

                                 //block length :means how many bytes in a block
                 in_BlockLength,
                 
                                 //to from receiver_FIFO
                 in_rFIFOFull,
                         out_rxDataToFIFO_r,
                 out_ReceiverWe,
                                 
                                 
                                 // to or from transmitter_FIFO
                 in_txDataFromTxFIFO,
                 in_TransmitFIFOEmpty, 
                         out_TransmitRead_r,        //the transmit shift register ask to read the data from the txFIFO

                                 //overtime signals     to set the status register in the APB_IF 
                 out_BWT_OvertimeIndicate_r,  //BWT
                 out_CWT_OvertimeIndicate_r,  //CWT
                 out_ATR_overtimeIndicator_r,
                 out_ATR_exceed9600ETUIndicator_r,
                 out_character_OvertimeIndicate_r,
                                 //parityError signal
                 out_ParityErrorIndicator_r,

                                 //FIFO error signals sent to APB_IF
                 out_TransmitterEmptyIndictor,                 
                 out_OverrunErrorIndicator_r,
                                 
                                 //input signal  from APB_IF to reset the overtime counters
                 in_readStatusRegister
                );

input clk_div;
input rst_preset_n_a;
input [1:0] indicate;   //01 read  ;  10 write;  00  idle;
input ColdEnable;
input WarmEnable;
input StateOfCard;
input T;
input  [7:0] WI;
input [15:0] F;
input [3:0]  D;
input [7:0] in_N;
input TS;
input [7:0] in_BlockLength;
input [3:0] in_BWI;
input [3:0] in_CWI;
input [7:0] in_BGT;
input [7:0] in_txDataFromTxFIFO;
input in_rFIFOFull;

input serial_in;
output serial_out;
output direction;
output Reset;
output out_ReceiverWe;
input in_TransmitFIFOEmpty;
output out_TransmitterEmptyIndictor;
output out_TransmitRead_r;     //the transmit shift register ask to read the data from the txFIFO
output [7:0] out_rxDataToFIFO_r;
input in_readStatusRegister;
output out_OverrunErrorIndicator_r;
output out_BWT_OvertimeIndicate_r;
output out_CWT_OvertimeIndicate_r;
output out_ATR_overtimeIndicator_r;
output out_ATR_exceed9600ETUIndicator_r;
output out_ParityErrorIndicator_r;
output out_character_OvertimeIndicate_r; 


parameter  DEFAULT_ETU =    5'b1010 ;
//parameter  COUNT4      =    22'b1101100111110111111111 ;
parameter  COUNT4      =    3'b101;

reg [5:0] current_state;

reg serial_out;
reg direction;
reg Reset;


///////////////overtime indicate register
reg out_ATR_overtimeIndicator_r;
reg out_ATR_exceed9600ETUIndicator_r;
reg out_BWT_OvertimeIndicate_r;
reg out_CWT_OvertimeIndicate_r;
reg out_ParityErrorIndicator_r;
reg out_character_OvertimeIndicate_r;
/////////////////////////////////////////

//counter
reg [17:0] COUNT;
reg [8:0] count1;          //400 clk
//reg [8:0] count11;          //400 clk
reg [15:0] count2;
//reg [8:0] count3;          //372 used in state receiver ATR Attention!!!
reg [4:0] count3;
reg [21:0] count4;         //9600ETU
reg [17:0] count5;         //character_receiver_ETU
reg [1:0] count10;
reg [2:0] rbit_counter_r;   //8 bit data
reg [2:0] bit_counter_r;   //8 bit transfer data
reg [4:0] character_number;
reg [20:0] character_transfer_overtime_r;  //960*F*WI
reg [24:0] count6;
reg [13:0] BWT_counter;
reg [13:0] count7;
reg [5:0] CWT_counter;
reg [5:0] count8;
reg [7:0] BlockLength;
reg [7:0] N;
reg [3:0] BWI;
reg [3:0] CWI;
reg [7:0] BGT;

//////////////////////////////////////////////////
reg rparity_xor_r;
reg parity_xor_r; //used in character transmitted
reg rparity_r;
reg [7:0] rshift_r;   //a shift register
reg rf_push_r;        //a signal of push data to fifo
reg [6:0]shift_out_r;
reg  bit_out_r;
reg rf_push_q_r;
reg [7:0] out_rxDataToFIFO_r;
reg  out_TransmitRead_r;
reg out_TransmitterEmptyIndictor;
reg out_OverrunErrorIndicator_r;
reg B_C_sent;




///////////////////////////////////////////////////

wire count3_eq_halfcount3;
wire count3_eq_0;
//wire  [8:0] count3_minus_1;

wire count5_eq_halfcount5;
wire count5_eq_0;
//wire [17:0] count5_minus_1;

wire out_ReceiverWe;       //ask for write data to rx_FIFO

assign  count3_eq_halfcount3 = (count3 == (DEFAULT_ETU >>1));
assign  count3_eq_0 = (count3 == 9'b0);
//assign  count3_minus_1 = count3 - 1'b1;

assign  count5_eq_halfcount5 = (count5 == (COUNT>>1));
assign  count5_eq_0 = (count5 == 18'b0);
//assign  count5_minus_1 = count5 - 1'b1;

always @ (D or F)
  begin
    case(D)
    4'b0001:COUNT = F;
    4'b0010:COUNT = F>>1;
    4'b0011:COUNT = F>>2;
    4'b0100:COUNT = F>>3;
    4'b0101:COUNT = F>>4;
    4'b0110:COUNT = F>>5;   
    4'b1010:COUNT = F<<1;
    4'b1011:COUNT = F<<2;
    4'b1100:COUNT = F<<3;
    4'b1101:COUNT = F<<4;
    4'b1110:COUNT = F<<5;
    4'b1111:COUNT = F<<6;
    default: COUNT = F;
    endcase
  end

//CALCULATE BWT  
always @ (BWI)//960*2^BWI *etu
  begin
    case(BWI)
      4'b0000:BWT_counter = 14'b00001111000000;
      4'b0001:BWT_counter = 14'b00011110000000;
      4'b0010:BWT_counter = 14'b00111100000000;
      4'b0011:BWT_counter = 14'b01111000000000;
      4'b0100:BWT_counter = 14'b11110000000000;  
      default :  BWT_counter = 14'b11110000000000;
    endcase
  end

//CALCULATE CWT 
always @ (CWI)
  begin
    case(CWI)
      4'b0000:CWT_counter =6'b000001;
      4'b0001:CWT_counter =6'b000010;
      4'b0010:CWT_counter =6'b000100;
      4'b0011:CWT_counter =6'b001000;
      4'b0100:CWT_counter =6'b010000;
      4'b0101:CWT_counter =6'b100000;
      default:CWT_counter =6'b000001;
    endcase
  end

always @ (D or WI)      //character_transfer_overtime_r = 960 * D * WI  etu
  begin
        case(D)
        4'b0001:character_transfer_overtime_r = (10'b1111000000 * WI);
        4'b0010:character_transfer_overtime_r = (11'b11110000000 * WI);
        4'b0011:character_transfer_overtime_r = (12'b111100000000 * WI);
        4'b0100:character_transfer_overtime_r = (13'b1111000000000 * WI);
        4'b0101:character_transfer_overtime_r = (14'b11110000000000 * WI);
        4'b0110:character_transfer_overtime_r = (15'b111100000000000 * WI);   
        4'b1010:character_transfer_overtime_r = (9'b111100000 * WI);
        4'b1011:character_transfer_overtime_r = (8'b11110000 * WI);
        4'b1100:character_transfer_overtime_r = (7'b1111000 * WI);
        4'b1101:character_transfer_overtime_r = (6'b111100 * WI);
        4'b1110:character_transfer_overtime_r = (5'b11110 * WI);
        4'b1111:character_transfer_overtime_r = (4'b1111 * WI);
    default: character_transfer_overtime_r = 14'b10010110000000;
    endcase
  end  


     
    
always @(posedge clk_div or negedge rst_preset_n_a )
  begin
    if (!rst_preset_n_a )
      begin    
          ////////Indicator_r/////////////////////
          out_ATR_overtimeIndicator_r <=1'b0;
          out_ATR_exceed9600ETUIndicator_r <=1'b0;
          out_BWT_OvertimeIndicate_r <=1'b0;
          out_CWT_OvertimeIndicate_r <=1'b0;
          out_ParityErrorIndicator_r <=1'b0;
          out_character_OvertimeIndicate_r <=1'b0;   
                   
          ///////count/////////////////   
          count1 <= 9'b110001111;    //400
          //count11 <= 9'b110001111; 
          count2 <= 16'b1001110000111111;        //40000 clk
          count3 <= DEFAULT_ETU - 1'b1;         //372 -1  used in ATR
          count4 <= COUNT4;      //9600 ETU
          count5 <= 18'b0;          
          count6 <=21'b0 ;
          count7 <= 14'b0;
          count8 <= 6'b0;
		  count10 <= 2'b0;
          rbit_counter_r <= 3'b111;
          bit_counter_r <= 3'b111; 
          //////////////////////////////
          direction <= 1'b1;
          serial_out <= 1'b1;
          Reset <= 1'b1;          
          B_C_sent <= 1'b0;
          rshift_r <= 8'b0;
          rf_push_r <= 1'b0;
          out_rxDataToFIFO_r <= 8'b0;        
          rparity_xor_r <=  1'b0;
          rparity_r <=  1'b0; 
          shift_out_r <= 7'b0;
          bit_out_r  <= 1'b0;
          parity_xor_r <= 1'b0;
          out_TransmitRead_r<= 1'b0;  
          N <= 8'b0;
          BWI <= 4'b0100;
          CWI <= 4'b0001;
          BGT <= 8'b10110;
          BlockLength <= 8'b1;
		  current_state <= `IDLE;
		  character_number <= 'h0;
      end 
    else
      begin
      case(current_state)
      `IDLE:
        begin
          ////////Indicator_r/////////////////////
          out_ATR_overtimeIndicator_r <=1'b0;
          out_ATR_exceed9600ETUIndicator_r <=1'b0;
          out_BWT_OvertimeIndicate_r <=1'b0;
          out_CWT_OvertimeIndicate_r <=1'b0;
          out_ParityErrorIndicator_r <=1'b0;
          out_character_OvertimeIndicate_r <=1'b0;   
                   
          ///////count/////////////////   
          count1 <= 9'b110001111;    //400
          //count11 <= 9'b110001111;
          count2 <= 16'b1001110000111111;        //40000 clk
          count3 <= DEFAULT_ETU -1'b1;         //372 -1  used in ATR
          count4 <= COUNT4;      //9600 ETU
          count5 <= COUNT -1'b1;          
          count6 <= character_transfer_overtime_r;
          count7 <= BWT_counter;
          count8 <= CWT_counter;
		  count10 <= 2'b11;
          rbit_counter_r <= 3'b111;
          bit_counter_r <= 3'b111; 
          direction <= 1'b1;
          Reset <= 1'b1;          
          B_C_sent <= 1'b0;
          rshift_r <= 8'b0;
          rf_push_r <= 1'b0;
          out_rxDataToFIFO_r <= 8'b0;
		  serial_out <= 1'b1;

          N <= in_N;
          BWI <= in_BWI;
          CWI <= in_CWI;
          BGT <= in_BGT;
          BlockLength <= in_BlockLength;
        //////////////////////////////////////////
          if (StateOfCard == 1'b1)
            begin
              if (WarmEnable || ColdEnable)
                  current_state <= `RESET_SET0;
			  else	
                if (indicate == 2'b00)
                  current_state <= `IDLE;
              else
                if ((indicate == 2'b01)&&(T ==1'b0))
                  current_state <= `CHARACTER_RECEIVER_WAIT_START;
              else
                if ((indicate == 2'b10)&&(T ==1'b0))
                  current_state <= `CHARACTER_TRANSMITTER_PREPARE;
              else
                if ((indicate == 2'b01)&&(T ==1'b1))
                  current_state <= `BLOCK_RECEIVER_GET_CWT_BWT;
              else 
                if ((indicate == 2'b10)&&(T ==1'b1))
                  current_state <= `BLOCK_TRANSMITTER_PREPARE;
            end   //end  if (StateOfCard == 1'b1)
           
           character_number <= 5'b11111 ; //32 WORD at most
         
       end   //end IDLE  

      `RESET_SET0:   
        begin     
          if (count1 == 3'h0)  //400 clk
            begin
              Reset <= 1'b1;
              serial_out <= 1'b1;
              direction <= 1'b0;              
//            current_state <= `RESET_HOLD;
              current_state <= `RESET_WAIT_ATR;
              count1 <= 9'b110001111;
            end   
          else                     
            begin
              Reset <= 1'b0;
              serial_out <= 1'b1; 
              direction <= 1'b0;
              current_state <= `RESET_SET0;        
            end           
          count1 <= count1 - 1'b1;
        end
/*          
      `RESET_HOLD:     
        begin
          if (count11 == 3'h0)  //400 clk 
            begin
              Reset <= 1'b1;
              serial_out <= 1'b1;   //I/O line can't set value to input
              count11 <= 9'b110001111;
              direction <= 1'b1;             
              current_state <= `RESET_WAIT_ATR;
            end  
    
          else   
            begin
              Reset <= 1'b1;
              serial_out <= 1'b1; 
              direction <= 1'b0;              
              current_state <= `RESET_HOLD;  
              count11 <= count11 - 1'b1;                    
            end                
        end
*/                
      `RESET_WAIT_ATR: 
        begin
          if (count2 == 4'h0)
            begin
              out_ATR_overtimeIndicator_r <= 1'b1;          //overtime register,check whether the card can provide any response
              if(in_readStatusRegister)
                begin
                  out_ATR_overtimeIndicator_r <= 1'b0;
                  current_state <= `IDLE; 
                end              
            end
          else
              begin