halgenfuns.c

CC2500的接受、发送数据包模块的库函数

//  ARGUMENTS:
//      BYTE addr
//          Address of the first CCxxx0 register to be accessed.
//      BYTE *buffer
//          Array of bytes to be written into a corresponding range of
//          CCxx00 registers, starting by the address specified in _addr_.
//      BYTE count
//          Number of bytes to be written to the subsequent CCxxx0 registers.   
//-------------------------------------------------------------------------------------------------------
void halSpiWriteBurstReg(BYTE addr, BYTE *buffer, BYTE count) {
    UINT8 i;
    SPI_CS = 0;
    while (SPI_SO);
    SPI0DAT = addr | WRITE_BURST;
    SPIF=0;
    while(!SPIF); 
    for (i = 0; i < count; i++) {
        SPI0DAT = buffer[i];
        SPIF=0;
    	while(!SPIF);
    }
    SPI_CS = 1;
}// halSpiWriteBurstReg

//-------------------------------------------------------------------------------------------------------
//  void RfWriteRfSettings(RF_SETTINGS *pRfSettings)
//
//  DESCRIPTION:
//      This function is used to configure the CC2500 based on a given rf setting
//
//  ARGUMENTS:
//      RF_SETTINGS *pRfSettings
//          Pointer to a struct containing rf register settings
//-------------------------------------------------------------------------------------------------------
void halRfWriteRfSettings(RF_SETTINGS *pRfSettings) {

	BYTE num,i;
    // Write register settings
	num = sizeof(RF_SETTINGS);
	for(i=0;i<num;i+=2){
		halSpiWriteReg(pRfSettings->a[i],pRfSettings->a[i+1]);
	}
}// halRfWriteRfSettings

void halverifyRfWriteRfSettings(RF_SETTINGS *pRfSettings) {

	BYTE num,i,ch;
    // Write register settings
	num = sizeof(RF_SETTINGS);
	for(i=0;i<num;i+=2){
		ch=halSpiReadReg(pRfSettings->a[i]);
		UART_SendAChar(pRfSettings->a[i]);
		UART_SendAChar(ch);
	}
}// halRfWriteRfSettings


//-------------------------------------------------------------------------------------------------------
//  BOOL halRfReceivePacket(BYTE *rxBuffer, UINT8 *length)
//
//  DESCRIPTION: 
//      This function can be used to receive a packet of variable packet length (first byte in the packet
//      must be the length byte). The packet length should not exceed the RX FIFO size.
//      To use this function, GD00 must be configured to be asserted when sync word is sent and 
//      de-asserted at the end of the packet => halSpiWriteReg(CCxxx0_IOCFG0, 0x06);
//      Also, APPEND_STATUS in the PKTCTRL1 register must be enabled.
//      The function implements polling of GDO0. First it waits for GD00 to be set and then it waits
//      for it to be cleared.
//      After the GDO0 pin has been de-asserted, the RXBYTES register is read to make sure that there
//      are bytes in the FIFO. This is because the GDO signal will indicate sync received even if the
//      FIFO is flushed due to address filtering, CRC filtering, or packet length filtering. 
//  
//  ARGUMENTS:
//      BYTE *rxBuffer
//          Pointer to the buffer where the incoming data should be stored
//      UINT8 *length
//          Pointer to a variable containing the size of the buffer where the incoming data should be
//          stored. After this function returns, that variable holds the packet length.
//          
//  RETURN VALUE:
//      BOOL
//          TRUE:   CRC OK
//          FALSE:  CRC NOT OK (or no packet was put in the RX FIFO due to filtering)
//
//  REVISION:
//		 
//-------------------------------------------------------------------------------------------------------
BOOL halRfReceivePacket(BYTE *rxBuffer, UINT8 *length) {
    BYTE k,status[2];
    UINT8 packetLength;

    halSpiStrobe(CCxxx0_SRX);

    // Wait for GDO0 to be set -> sync received
 	LED2=0;
    while (!GDO0_PIN);

    // Wait for GDO0 to be cleared -> end of packet
    while (GDO0_PIN);
	LED2=1;

    // This status register is safe to read since it will not be updated after
    // the packet has been received (See the CC11xx and 25xx Errata Note)

    if (( halSpiReadStatus(CCxxx0_RXBYTES)& BYTES_IN_RXFIFO)) {

        // Read length byte
        packetLength = halSpiReadReg(CCxxx0_RXFIFO);
    
        // Read data from RX FIFO and store in rxBuffer
        if (packetLength <= *length) {
            halSpiReadBurstReg(CCxxx0_RXFIFO, rxBuffer, packetLength); 
            *length = packetLength;
        
            // Read the 2 appended status bytes (status[0] = RSSI, status[1] = LQI)
            halSpiReadBurstReg(CCxxx0_RXFIFO, status, 2); 
        
            // MSB of LQI is the CRC_OK bit
            return (status[LQI] & CRC_OK);
        } else {
            *length = packetLength;

            // Make sure that the radio is in IDLE state before flushing the FIFO
            // (Unless RXOFF_MODE has been changed, the radio should be in IDLE state at this point) 
            halSpiStrobe(CCxxx0_SIDLE);

            // Flush RX FIFO
            halSpiStrobe(CCxxx0_SFRX);

            return FALSE;
        } 
    } else
        return FALSE;
}// halRfReceivePacket


//-------------------------------------------------------------------------------------------------------
//  void halRfSendPacket(BYTE *txBuffer, UINT8 size)
//
//  DESCRIPTION:
//      This function can be used to transmit a packet with packet length up to 63 bytes.
//      To use this function, GD00 must be configured to be asserted when sync word is sent and 
//      de-asserted at the end of the packet => halSpiWriteReg(CCxxx0_IOCFG0, 0x06);
//      The function implements polling of GDO0. First it waits for GD00 to be set and then it waits
//      for it to be cleared.  
//      
//  ARGUMENTS:
//      BYTE *txBuffer
//          Pointer to a buffer containing the data that are going to be transmitted
//
//      UINT8 size
//          The size of the txBuffer
//
//  REVISION:
// 		2007-10-25 Add FLUSH TX_FIFO before write data to TX_FIFO.
//				   Comment the working on "2007-10-23", find the function work normally, then cancel it.
//		2007-10-23 Add Redo "STX" function after the first time STX command.
//					 "i = halSpiReadStatus(CCxxx0_MARCSTATE);  if(i==0x0F) halSpiStrobe(CCxxx0_STX);"
//-------------------------------------------------------------------------------------------------------
void halRfSendPacket(BYTE *txBuffer, UINT8 size) {

	BYTE i;
    halSpiStrobe(CCxxx0_SFTX);
	halWait(10);

    halSpiWriteBurstReg(CCxxx0_TXFIFO, txBuffer, size);
	halWait(10);

    halSpiStrobe(CCxxx0_STX);
	halWait(10);

    // Wait for GDO0 to be set -> sync transmitted
	LED2=0;
    while (!GDO0_PIN);

    // Wait for GDO0 to be cleared -> end of packet
    while (GDO0_PIN);
	LED2=1;

    halSpiStrobe(CCxxx0_SIDLE);
}// halRfSendPacket




// Chipcon
// Product = CC2500
// Chip version = E   (VERSION = 0x03)
// Crystal accuracy = 10 ppm
// X-tal frequency = 26 MHz
// RF output power = 0 dBm
// RX filterbandwidth = 406.250000 kHz
// Deviation = 38 kHz
// Datarate = 2.398968 kBaud
// Modulation = (0) 2-FSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 2433.599762 MHz
// Channel spacing = 199.951172 kHz
// Channel number = 3
// Optimization = Sensitivity
// Sync mode = (3) 30/32 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (1) Variable length packets, packet length configured by the first received byte after sync word.
// Packetlength = 255
// Preamble count = (6) 16 bytes
// Append status = 1
// Address check = (0) No address check
// FIFO autoflush = 0
// Device address = 0
// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
// GDO2 signal selection = (41) CHIP_RDY
RF_SETTINGS code rfSettings = {
    0x0B, 0x08,   // FSCTRL1   Frequency synthesizer control.
    0x0C, 0x00,   // FSCTRL0   Frequency synthesizer control.
    0x0D, 0x5D,   // FREQ2     Frequency control word, high byte.
    0x0E, 0x93,   // FREQ1     Frequency control word, middle byte.
    0x0F, 0xB1,   // FREQ0     Frequency control word, low byte.
    0x10, 0x46,   // MDMCFG4   Modem configuration.
    0x11, 0x83,   // MDMCFG3   Modem configuration.
    0x12, 0x03,   // MDMCFG2   Modem configuration.
    0x13, 0x62,   // MDMCFG1   Modem configuration.
    0x14, 0xF8,   // MDMCFG0   Modem configuration.
    0x0A, 0x03,   // CHANNR    Channel number.
    0x15, 0x44,   // DEVIATN   Modem deviation setting (when FSK modulation is enabled).
    0x21, 0x56,   // FREND1    Front end RX configuration.
    0x22, 0x10,   // FREND0    Front end RX configuration.
    0x18, 0x18,   // MCSM0     Main Radio Control State Machine configuration.
    0x19, 0x16,   // FOCCFG    Frequency Offset Compensation Configuration.
    0x1A, 0x6C,   // BSCFG     Bit synchronization Configuration.
    0x1B, 0x03,   // AGCCTRL2  AGC control.
    0x1C, 0x40,   // AGCCTRL1  AGC control.
    0x1D, 0x91,   // AGCCTRL0  AGC control.
    0x23, 0xA9,   // FSCAL3    Frequency synthesizer calibration.
    0x24, 0x0A,   // FSCAL2    Frequency synthesizer calibration.
    0x25, 0x00,   // FSCAL1    Frequency synthesizer calibration.
    0x26, 0x11,   // FSCAL0    Frequency synthesizer calibration.
    0x29, 0x59,   // FSTEST    Frequency synthesizer calibration.
    0x2C, 0x88,   // TEST2     Various test settings.
    0x2D, 0x31,   // TEST1     Various test settings.
    0x2E, 0x0B,   // TEST0     Various test settings.
    0x00, 0x29,   // IOCFG2    GDO2 output pin configuration.
    0x02, 0x06,   // IOCFG0D   GDO0 output pin configuration. Refer to SmartRF