sim5206.h

uCOSII code for Coldfire processor

/**********************************************************************
*   MCF5206 ColdFire Assembly Header File                             *
*                                                                     *
*   Developed by       : Motorola                                     *
*                        Imaging and Storage Systems Division         *
*                        Austin, TX                                   *
*                                                                     *
**********************************************************************/
 
#define MBASE 0x10000000    // Module Base Address

 
typedef struct
{
  unsigned short csar;        /* Chip-Select X Base Address Register, 16-bit, R/W (00-01) */
  unsigned char pack01[2];    /* 02-03 */
  unsigned long csmr;         /* Chip-Select X Address Mask Register, 32-bit, R/W (04-07) */
  unsigned char pack02[2];    /* 08-09 */
  unsigned short cscr;        /* Chip-Select X Control Register, 16-bit, R/W (0A-0B) */
} csstruct;


typedef struct
{
  unsigned short tmr;         /* TIMERx Mode Register, 16-bit, R/W (00-01) */
  unsigned char pack01[2];    /* 02-03 */
  unsigned short trr;         /* TIMERx Mode Register, 16-bit, R/W (04-05) */
  unsigned char pack02[2];    /* 06-07 */
  unsigned short tcr;         /* TIMERx Capture Register, 16-bit, R (08-09) */
  unsigned char pack03[2];    /* 0A-0B */
  unsigned short tcn;         /* TIMERx Counter, 16-bit, R/W (0C-0D) */
  unsigned char pack04[3];    /* 0E-10 */
  unsigned char ter;          /* TIMERx Event Register, 8-bit, R/W (11) */
} tmrstruct;
  

typedef struct
{
  unsigned char umr;          /* UARTx Mode Register, 8-bit, R/W (00) */
  unsigned char pack01[3];    /* 01-03 */
  unsigned char usr;          /* UARTx Status Register, 8-bit, R (04) */
  unsigned char pack02[7];    /* 05-0B */
  unsigned char urbuf;        /* UARTx Receiver Buffer, 8-bit, R (0C) */
  unsigned char pack03[3];    /* 0D-0F */
  unsigned char uipcr;        /* UARTx Input Port Change Register, 8-bit, R (10) */
  unsigned char pack04[3];    /* 11-13 */
  unsigned char uisr;         /* UARTx Interrupt Status Register, 8-bit, R (14) */
  unsigned char pack05[3];    /* 15-17 */
  unsigned char ubg1;         /* UARTx Baud Rate Generator PreScale MSB, 8-bit, R/W (18) */
  unsigned char pack06[3];    /* 19-1B */
  unsigned char ubg2;         /* UARTx Baud Rate Generator PreScale LSB, 8-bit, R/W (1C) */
  unsigned char pack07[19];   /* 1D-2F */
  unsigned char uivr;         /* UARTx Interrupt Vector Register, 8-bit, R/W (30) */
  unsigned char pack08[3];    /* 31-33 */
  unsigned char uip;          /* UARTx Input Port Register, 8-bit, R (34) */
} UARTReadStruct;

typedef struct
{
  unsigned char umr;          /* UARTx Mode Register, 8-bit, R/W (00) */
  unsigned char pack01[3];    /* 01-03 */
  unsigned char ucsr;         /* UART1 Clock Select Register, 8-bit, W (04) */
  unsigned char pack02[3];    /* 05-07 */
  unsigned char ucr;          /* UARTx Command Register, 8-bit, W (08) */
  unsigned char pack2a[3];    /* 09-0B */
  unsigned char utbuf;        /* UARTx Transmitter Buffer, 8-bit, W (0C) */
  unsigned char pack03[3];    /* 0D-0F */
  unsigned char uacr;         /* UARTx Auxiliary Control Register, 8-bit, W (10) */
  unsigned char pack04[3];    /* 11-13 */
  unsigned char uimr;         /* UARTx Interrupt Mask Register, 8-bit, W (14) */
  unsigned char pack05[3];    /* 15-17 */
  unsigned char ubg1;         /* UARTx Baud Rate Generator PreScale MSB, 8-bit, R/W (18) */
  unsigned char pack06[3];    /* 19-1B */
  unsigned char ubg2;         /* UARTx Baud Rate Generator PreScale LSB, 8-bit, R/W (1C) */
  unsigned char pack07[19];   /* 1D-2F */
  unsigned char uivr;         /* UARTx Interrupt Vector Register, 8-bit, R/W (30) */
  unsigned char pack08[7];    /* 31-37 */
  unsigned char uop1;         /* UARTx Output Port Bit Set Command, 8-bit, W (38) */
  unsigned char pack09[3];    /* 39-3B */
  unsigned char uop0;         /* UARTx Output Port Bit Reset Command, 8-bit, W (3C) */
} UARTWriteStruct;

typedef union
{
  UARTReadStruct  read;
  UARTWriteStruct write; 
  unsigned char pack01[0x40];  
} uartstruct;


typedef struct
{
  unsigned char madr;         /* M-BUS Address Register, 8-bit, R/W (00) */
  unsigned char pack01[3];    /* 01-03 */
  unsigned char mfdr;         /* M-BUS Frequency Divider Register, 8-bit, R/W (04) */
  unsigned char pack02[3];    /* 05-07 */
  unsigned char mbcr;         /* M-BUS Control Register, 8-bit, R/W (08) */
  unsigned char pack03[3];    /* 09-0B */
  unsigned char mbsr;         /* M-BUS Status Register, 8-bit, R/W (0C) */
  unsigned char pack04[3];    /* 0D-0F */
  unsigned char mbdr;         /* M-BUS Data I/O Register, 8-bit, R/W (10) */
} mbusstruct;


//* System Integration Module
 
//* Example: 
//*          move.b   #value,D0    |Load data register with value
//*          move.b   D0,SIMR      |Place value into register

typedef struct
{
  unsigned char pack01[3];    /* 000-002 */
  unsigned char simr;         /* SIM Configuration Register, 8-bit, R/W (003) */
  unsigned char pack02[0x10]; /* 004-013 */
  unsigned char icr1;         /* Interrupt Control Register Ext1, 8-bit, R/W (014) */
  unsigned char icr2;         /* Interrupt Control Register Ext2, 8-bit, R/W (015) */
  unsigned char icr3;         /* Interrupt Control Register Ext3, 8-bit, R/W (016) */
  unsigned char icr4;         /* Interrupt Control Register Ext4, 8-bit, R/W (017) */
  unsigned char icr5;         /* Interrupt Control Register Ext5, 8-bit, R/W (018) */
  unsigned char icr6;         /* Interrupt Control Register Ext6, 8-bit, R/W (019) */
  unsigned char icr7;         /* Interrupt Control Register Ext7, 8-bit, R/W (01A) */
  unsigned char icr8;         /* Interrupt Control Register Ext8, 8-bit, R/W (01B) */
  unsigned char icr9;         /* Interrupt Control Register Ext9, 8-bit, R/W (01C) */
  unsigned char icr10;        /* Interrupt Control Register Ext10, 8-bit, R/W (01D) */
  unsigned char icr11;        /* Interrupt Control Register Ext11, 8-bit, R/W (01E) */
  unsigned char icr12;        /* Interrupt Control Register Ext12, 8-bit, R/W (01F) */
  unsigned char icr13;        /* Interrupt Control Register Ext13, 8-bit, R/W (020) */
  unsigned char pack03[0x15]; /* 021-035 */
  unsigned short imr;         /* Interrupt Mask Register, 32-bit, R/W (036-037) */
  unsigned char pack3a[2];    /* 038-039 */
  unsigned short ipr;         /* Interrupt Pending Register, 32-bit, R (03A-3B) */
  unsigned char pack04[4];    /* 03C-03F */
  unsigned char rsr;          /* Reset Status Register, 8-bit, R/W (040) */
  unsigned char sypcr;        /* System Protection Control Register, 8-bit, R/W (041) */
  unsigned char swivr;        /* Software Watchdog Interrupt Vector Register, 8-bit, W (042) */
  unsigned char swsr;         /* Software Watchdog Service Register, 8-bit, W (043) */
  unsigned char pack05[2];    /* 044-045 */


/** DRAM Controller Registers **/
  
  unsigned short dcrr;        /* DRAM Controller Refresh Register, 16-bit, R/W (046-047) */
  unsigned char pack06[2];    /* 048-049 */
  unsigned short dctr;        /* DRAM Controller Timing Register, 16-bit, R/W (04A-04B) */

  unsigned short dcar0;       /* DRAM Controller Bank 0 Address Register, 16-bit, R/W (04C-04D) */
  unsigned char pack07[2];    /* 04E-04F */
  unsigned long dcmr0;        /* DRAM Controller Bank 0 Mask Register, 32-bit, R/W (050-053) */
  unsigned char pack08[3];    /* 054-056 */
  unsigned char dccr0;        /* DRAM Controller Bank 0 Control Register, 8-bit, R/W (057) */

  unsigned short dcar1;       /* DRAM Controller Bank 1 Address Register, 16-bit, R/W (058-059) */
  unsigned char pack09[2];    /* 05A-05B */
  unsigned long dcmr1;        /* DRAM Controller Bank 1 Mask Register, 32-bit, R/W (05C-05F) */
  unsigned char pack10[3];    /* 060-062 */
  unsigned char dccr1;        /* DRAM Controller Bank 1 Control Register, 8-bit, R/W (063) */
  

/** Chip Select Registers **/
  
  csstruct cs[8];             /* Chip-Select registers (064-0C3) */
  unsigned char pack11[2];    /* 0C4-0C5 */
  unsigned short dmcr;        /* Default Memory Control Register, 16-bit, R/W (0C6-0C7) */
  unsigned char pack12[3];    /* 0C8-CA */


/** General Purpose I/O **/

  unsigned char par;          /* Pin Assignment Register, 8-bit, R/W (0CB) */
  unsigned char pack13[0x34]; /* 0CC-0FF */
  tmrstruct timer1;           /* Timer 1 Module (100-111) */
  unsigned char pack14[0xE];  /* 112-11F */
  tmrstruct timer2;           /* Timer 2 Module (120-131) */
  unsigned char pack15[0xE];  /* 132-13F */
  uartstruct uart1;           /* UART 1 Module (140-17F) */
  uartstruct uart2;           /* UART 2 Module (180-1BF) */
  unsigned char pack18[5];    /* 1C0-1C4 */
  unsigned char ppddr;        /* Port A Data Direction Register, 8-bit, R/W (1C5) */
  unsigned char pack19[3];    /* 1C6-1C8 */
  unsigned char ppdat;        /* Port A Data Direction Register, 8-bit, R/W (1C9) */
  unsigned char pack20[0x16]; /* 1CA-1DF */
  mbusstruct mbus;

} SIM5206;


/*
|IO stuff
.set PAR ,    MBASE+0x00CB  |Pin Assignment Register, 8-bit, R/W
.set PPDDR,   MBASE+0x01C5  |Port A Data Direction Register, 8-bit, R/W
.set PPDAT,   MBASE+0x01C9  |Port A Data Register, 8-bit, R/W

|* Timer Registers

|* Timer 1

.set TMR1,    MBASE+0x0100  |TIMER1 Mode Register, 16-bit, R/W
.set TRR1,    MBASE+0x0104  |TIMER1 TIMER1 Mode Register, 16-bit, R/W
.set TCR1,    MBASE+0x0108  |TIMER1 Capture Register, 16-bit, R
.set TCN1,    MBASE+0x010C  |TIMER1 Counter, 16-bit, R/W
.set TER1,    MBASE+0x0111  |TIMER1 Event Register, 8-bit, R/W

|* Timer 2

.set TMR2,    MBASE+0x0120  |TIMER2 Mode Register, 16-bit, R/W
.set TRR2,    MBASE+0x0124  |TIMER2 Mode Register, 16-bit, R/W
.set TCR2,    MBASE+0x0128  |TIMER2 Capture Register, 16-bit, R
.set TCN2,    MBASE+0x012C  |TIMER2 Counter, 16-bit, R/W
.set TER2,    MBASE+0x0131  |TIMER2 Event Register, 8-bit, R/W

|* Serial Module Registers

|* UART1

.set UMR1,   MBASE+0x0140  |UART1 Mode Register, 8-bit, R/W
.set USR1,   MBASE+0x0144  |UART1 Status Register, 8-bit, R
.set UCSR1,  MBASE+0x0144  |UART1 Clock Select Register, 8-bit, W
.set UCR1,   MBASE+0x0148  |UART1 Command Register, 8-bit, W
.set URBUF1, MBASE+0x014C  |UART1 Receiver Buffer, 8-bit, R
.set UTBUF1, MBASE+0x014C  |UART1 Transmitter Buffer, 8-bit, W
.set UISR1,  MBASE+0x0150  |UART1 Input Port Change Register, 8-bit, R
.set UACR1,  MBASE+0x0150  |UART1 Auxiliary Control Register, 8-bit, W
.set UIR1,   MBASE+0x0154  |UART1 Interrupt Status Register, 8-bit, R
.set UIMR1,  MBASE+0x0154  |UART1 Interrupt Mask Register, 8-bit, W (changed from UMR1)
.set UBG11,  MBASE+0x0158  |UART1 Baud Rate Generator PreScale MSB, 8-bit, W
.set UBG21,  MBASE+0x015C  |UART1 Baud Rate Generator PreScale LSB, 8-bit, W
.set UIVR1,  MBASE+0x0170  |UART1 Interrupt Vector Register, 8-bit, R/W
.set UIP1,   MBASE+0x0174  |UART1 Input Port Register, 8-bit, R
.set UOP11,  MBASE+0x0178  |UART1 Output Port Bit Set Command, 8-bit, W
.set UOP01,  MBASE+0x017C  |UART1 Output Port Bit Reset Command, 8-bit, W

|* UART2

.set UMR2,   MBASE+0x0180  |UART2 Mode Register, 8-bit, R/W
.set USR2,   MBASE+0x0184  |UART2 Status Register, 8-bit, R
.set UCSR2,  MBASE+0x0184  |UART2 Clock Select Register, 8-bit, W
.set UCR2,   MBASE+0x0188  |UART2 Command Register, 8-bit, W
.set URBUF2, MBASE+0x018C  |UART2 Receiver Buffer, 8-bit, R
.set UTBUF2, MBASE+0x018C  |UART2 Transmitter Buffer, 8-bit, W
.set UISR2,  MBASE+0x0190  |UART2 Input Port Change Register, 8-bit, R
.set UACR2,  MBASE+0x0190  |UART2 Auxiliary Control Register, 8-bit, W
.set UIR2,   MBASE+0x0194  |UART2 Interrupt Status Register, 8-bit, R
.set UIMR2,  MBASE+0x0194  |UART2 Interrupt Mask Register, 8-bit, W (changed from UMR2)
.set UBG12,  MBASE+0x0198  |UART1 Baud Rate Generator PreScale MSB, 8-bit, W
.set UBG22,  MBASE+0x019C  |UART2 Baud Rate Generator PreScale LSB, 8-bit, W
.set UIVR2,  MBASE+0x01B0  |UART2 Interrupt Vector Register, 8-bit, R/W
.set UIP2,   MBASE+0x01B4  |UART2 Input Port Register, 8-bit, R
.set UOP12,  MBASE+0x01B8  |UART2 Output Port Bit Set Command, 8-bit, W
.set UOP02,  MBASE+0x01BC  |UART2 Output Port Bit Reset Command, 8-bit, W

|* M-BUS Registers

.set MADR,   MBASE+0x01E0  |M-BUS Address Register, 8-bit, R/W
.set MFDR,   MBASE+0x01E4  |M-BUS Frequency Divider Register, 8-bit, R/W
.set MBCR,   MBASE+0x01E8  |M-BUS Control Register, 8-bit, R/W
.set MBSR,   MBASE+0x01EC  |M-BUS Status Register, 8-bit, R/W
.set MBDR,   MBASE+0x01F0  |M-BUS Data I/O Register, 8-bit, R/W


*/