📄 iolpc2148.h
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#endif /* __IAR_SYSTEMS_ICC__ */
/* Declarations common to compiler and assembler **************************/
/***************************************************************************
**
** System control block
**
***************************************************************************/
__IO_REG32_BIT( EXTINT , 0xE01FC140 , __READ_WRITE , __extint_bits );
__IO_REG32_BIT( EXTWAKE , 0xE01FC144 , __READ_WRITE , __extwake_bits );
__IO_REG32_BIT( EXTMODE , 0xE01FC148 , __READ_WRITE , __extmode_bits );
__IO_REG32_BIT( EXTPOLAR , 0xE01FC14C , __READ_WRITE , __extpolar_bits );
__IO_REG32_BIT( MEMMAP , 0xE01FC040 , __READ_WRITE , __memmap_bits );
__IO_REG32_BIT( PLLCON , 0xE01FC080 , __READ_WRITE , __pllcon_bits );
__IO_REG32_BIT( PLLCFG , 0xE01FC084 , __READ_WRITE , __pllcfg_bits );
__IO_REG32_BIT( PLLSTAT , 0xE01FC088 , __READ , __pllstat_bits );
__IO_REG32_BIT( PLLFEED , 0xE01FC08C , __WRITE , __pllfeed_bits );
__IO_REG32_BIT( PCON , 0xE01FC0C0 , __READ_WRITE , __pcon_bits );
__IO_REG32_BIT( PCONP , 0xE01FC0C4 , __READ_WRITE , __pconp_bits );
__IO_REG32_BIT( VPBDIV , 0xE01FC100 , __READ_WRITE , __vpbdiv_bits );
__IO_REG32_BIT( RSIR , 0xE01FC180 , __READ_WRITE , __rsir_bits );
__IO_REG32( SCCSPR , 0xE01FC184 , __READ_WRITE );
/***************************************************************************
**
** MAM
**
***************************************************************************/
__IO_REG32_BIT( MAMCR , 0xE01FC000 , __READ_WRITE , __mamcr_bits );
__IO_REG32_BIT( MAMTIM , 0xE01FC004 , __READ_WRITE , __mamtim_bits );
/***************************************************************************
**
** VIC
**
***************************************************************************/
__IO_REG32_BIT( VICIRQStatus , 0xFFFFF000 , __READ , __vicint_bits );
__IO_REG32_BIT( VICFIQStatus , 0xFFFFF004 , __READ , __vicint_bits );
__IO_REG32_BIT( VICRawIntr , 0xFFFFF008 , __READ , __vicint_bits );
__IO_REG32_BIT( VICIntSelect , 0xFFFFF00C , __READ_WRITE , __vicint_bits );
__IO_REG32_BIT( VICIntEnable , 0xFFFFF010 , __READ_WRITE , __vicint_bits );
__IO_REG32_BIT( VICIntEnClear , 0xFFFFF014 , __WRITE , __vicint_bits );
__IO_REG32_BIT( VICSoftInt , 0xFFFFF018 , __READ_WRITE , __vicint_bits );
__IO_REG32_BIT( VICSoftIntClear , 0xFFFFF01C , __WRITE , __vicint_bits );
__IO_REG32_BIT( VICProtection , 0xFFFFF020 , __READ_WRITE , __vicprotection_bits );
__IO_REG32( VICVectAddr , 0xFFFFF030 , __READ_WRITE );
__IO_REG32( VICDefVectAddr , 0xFFFFF034 , __READ_WRITE );
__IO_REG32( VICVectAddr0 , 0xFFFFF100 , __READ_WRITE );
__IO_REG32( VICVectAddr1 , 0xFFFFF104 , __READ_WRITE );
__IO_REG32( VICVectAddr2 , 0xFFFFF108 , __READ_WRITE );
__IO_REG32( VICVectAddr3 , 0xFFFFF10C , __READ_WRITE );
__IO_REG32( VICVectAddr4 , 0xFFFFF110 , __READ_WRITE );
__IO_REG32( VICVectAddr5 , 0xFFFFF114 , __READ_WRITE );
__IO_REG32( VICVectAddr6 , 0xFFFFF118 , __READ_WRITE );
__IO_REG32( VICVectAddr7 , 0xFFFFF11C , __READ_WRITE );
__IO_REG32( VICVectAddr8 , 0xFFFFF120 , __READ_WRITE );
__IO_REG32( VICVectAddr9 , 0xFFFFF124 , __READ_WRITE );
__IO_REG32( VICVectAddr10 , 0xFFFFF128 , __READ_WRITE );
__IO_REG32( VICVectAddr11 , 0xFFFFF12C , __READ_WRITE );
__IO_REG32( VICVectAddr12 , 0xFFFFF130 , __READ_WRITE );
__IO_REG32( VICVectAddr13 , 0xFFFFF134 , __READ_WRITE );
__IO_REG32( VICVectAddr14 , 0xFFFFF138 , __READ_WRITE );
__IO_REG32( VICVectAddr15 , 0xFFFFF13C , __READ_WRITE );
__IO_REG32_BIT( VICVectCntl0 , 0xFFFFF200 , __READ_WRITE , __vicvectcntl_bits );
__IO_REG32_BIT( VICVectCntl1 , 0xFFFFF204 , __READ_WRITE , __vicvectcntl_bits );
__IO_REG32_BIT( VICVectCntl2 , 0xFFFFF208 , __READ_WRITE , __vicvectcntl_bits );
__IO_REG32_BIT( VICVectCntl3 , 0xFFFFF20C , __READ_WRITE , __vicvectcntl_bits );
__IO_REG32_BIT( VICVectCntl4 , 0xFFFFF210 , __READ_WRITE , __vicvectcntl_bits );
__IO_REG32_BIT( VICVectCntl5 , 0xFFFFF214 , __READ_WRITE , __vicvectcntl_bits );
__IO_REG32_BIT( VICVectCntl6 , 0xFFFFF218 , __READ_WRITE , __vicvectcntl_bits );
__IO_REG32_BIT( VICVectCntl7 , 0xFFFFF21C , __READ_WRITE , __vicvectcntl_bits );
__IO_REG32_BIT( VICVectCntl8 , 0xFFFFF220 , __READ_WRITE , __vicvectcntl_bits );
__IO_REG32_BIT( VICVectCntl9 , 0xFFFFF224 , __READ_WRITE , __vicvectcntl_bits );
__IO_REG32_BIT( VICVectCntl10 , 0xFFFFF228 , __READ_WRITE , __vicvectcntl_bits );
__IO_REG32_BIT( VICVectCntl11 , 0xFFFFF22C , __READ_WRITE , __vicvectcntl_bits );
__IO_REG32_BIT( VICVectCntl12 , 0xFFFFF230 , __READ_WRITE , __vicvectcntl_bits );
__IO_REG32_BIT( VICVectCntl13 , 0xFFFFF234 , __READ_WRITE , __vicvectcntl_bits );
__IO_REG32_BIT( VICVectCntl14 , 0xFFFFF238 , __READ_WRITE , __vicvectcntl_bits );
__IO_REG32_BIT( VICVectCntl15 , 0xFFFFF23C , __READ_WRITE , __vicvectcntl_bits );
/***************************************************************************
**
** Pin connect block
**
***************************************************************************/
__IO_REG32_BIT( PINSEL0 , 0xE002C000 , __READ_WRITE , __pinsel0_bits );
__IO_REG32_BIT( PINSEL1 , 0xE002C004 , __READ_WRITE , __pinsel1_bits );
__IO_REG32( PINSEL2 , 0xE002C014 , __READ_WRITE );
/***************************************************************************
**
** GPIO
**
***************************************************************************/
__IO_REG32_BIT( IO0PIN , 0xE0028000 , __READ , __gpio_bits );
__IO_REG32_BIT( IO0SET , 0xE0028004 , __READ_WRITE , __gpio_bits );
__IO_REG32_BIT( IO0DIR , 0xE0028008 , __READ_WRITE , __gpio_bits );
__IO_REG32_BIT( IO0CLR , 0xE002800C , __WRITE , __gpio_bits );
__IO_REG32_BIT( IO1PIN , 0xE0028010 , __READ , __gpio_bits );
__IO_REG32_BIT( IO1SET , 0xE0028014 , __READ_WRITE , __gpio_bits );
__IO_REG32_BIT( IO1DIR , 0xE0028018 , __READ_WRITE , __gpio_bits );
__IO_REG32_BIT( IO1CLR , 0xE002801C , __WRITE , __gpio_bits );
/***************************************************************************
**
** UART0
**
***************************************************************************/
/* U0DLL, U0RBR and U0THR share the same address */
__IO_REG8( U0RBRTHR , 0xE000C000 , __READ_WRITE );
#define U0DLL U0RBRTHR
#define U0RBR U0RBRTHR
#define U0THR U0RBRTHR
/* U0DLM and U0IER share the same address */
__IO_REG8_BIT( U0IER , 0xE000C004 , __READ_WRITE , __uartier0_bits );
#define U0DLM U0IER
/* U0FCR and U0IIR share the same address */
__IO_REG8_BIT( U0FCR , 0xE000C008 , __READ_WRITE , __uartfcriir_bits );
#define U0IIR U0FCR
#define U0IIR_bit U0FCR_bit
__IO_REG8_BIT( U0LCR , 0xE000C00C , __READ_WRITE , __uartlcr_bits );
__IO_REG8_BIT( U0LSR , 0xE000C014 , __READ , __uartlsr_bits );
__IO_REG8( U0SCR , 0xE000C01C , __READ_WRITE );
__IO_REG8_BIT( U0TER , 0xE000C030 , __READ_WRITE , __uartter_bits );
/***************************************************************************
**
** UART1
**
***************************************************************************/
/* U1DLL, U1RBR and U1THR share the same address */
__IO_REG8( U1RBRTHR , 0xE0010000 , __READ_WRITE );
#define U1DLL U1RBRTHR
#define U1RBR U1RBRTHR
#define U1THR U1RBRTHR
/* U1DLM and U1IER share the same address */
__IO_REG8_BIT( U1IER , 0xE0010004 , __READ_WRITE , __uartier1_bits );
#define U1DLM U1IER
/* U1FCR and U1IIR share the same address */
__IO_REG8_BIT( U1FCR , 0xE0010008 , __READ_WRITE , __uartfcriir_bits );
#define U1IIR U1FCR
#define U1IIR_bit U1FCR_bit
__IO_REG8_BIT( U1LCR , 0xE001000C , __READ_WRITE , __uartlcr_bits );
__IO_REG8_BIT( U1MCR , 0xE0010010 , __READ_WRITE , __uartmcr_bits );
__IO_REG8_BIT( U1LSR , 0xE0010014 , __READ , __uartlsr_bits );
__IO_REG8_BIT( U1MSR , 0xE0010018 , __READ_WRITE , __uartmsr_bits );
__IO_REG8( U1SCR , 0xE001001C , __READ_WRITE );
__IO_REG8_BIT( U1TER , 0xE0010030 , __READ_WRITE , __uartter_bits );
/***************************************************************************
**
** I2C
**
***************************************************************************/
__IO_REG32_BIT( I20CONSET , 0xE001C000 , __READ_WRITE , __i2conset_bits );
__IO_REG32_BIT( I20STAT , 0xE001C004 , __READ , __i2stat_bits );
__IO_REG32_BIT( I20DAT , 0xE001C008 , __READ_WRITE , __i2dat_bits );
__IO_REG32_BIT( I20ADR , 0xE001C00C , __READ_WRITE , __i2adr_bits );
__IO_REG32_BIT( I20SCLH , 0xE001C010 , __READ_WRITE , __i2scl_bits );
__IO_REG32_BIT( I20SCLL , 0xE001C014 , __READ_WRITE , __i2scl_bits );
__IO_REG32_BIT( I20CONCLR , 0xE001C018 , __WRITE , __i2conclr_bits );
__IO_REG32_BIT( I21CONSET , 0xE005C000 , __READ_WRITE , __i2conset_bits );
__IO_REG32_BIT( I21STAT , 0xE005C004 , __READ , __i2stat_bits );
__IO_REG32_BIT( I21DAT , 0xE005C008 , __READ_WRITE , __i2dat_bits );
__IO_REG32_BIT( I21ADR , 0xE005C00C , __READ_WRITE , __i2adr_bits );
__IO_REG32_BIT( I21SCLH , 0xE005C010 , __READ_WRITE , __i2scl_bits );
__IO_REG32_BIT( I21SCLL , 0xE005C014 , __READ_WRITE , __i2scl_bits );
__IO_REG32_BIT( I21CONCLR , 0xE005C018 , __WRITE , __i2conclr_bits );
/***************************************************************************
**
** SPI
**
***************************************************************************/
__IO_REG32_BIT( S0SPCR , 0xE0020000 , __READ_WRITE , __spcr_bits );
__IO_REG32_BIT( S0SPSR , 0xE0020004 , __READ , __spsr_bits );
__IO_REG32_BIT( S0SPDR , 0xE0020008 , __READ_WRITE , __spdr_bits );
__IO_REG32_BIT( S0SPCCR , 0xE002000C , __READ_WRITE , __spccr_bits );
__IO_REG32_BIT( S0SPINT , 0xE002001C , __READ_WRITE , __spint_bits );
/***************************************************************************
**
** SSP
**
***************************************************************************/
__IO_REG32_BIT( SSPCR0 , 0xE0068000 , __READ_WRITE , __sspcr0_bits );
__IO_REG32_BIT( SSPCR1 , 0xE0068004 , __READ_WRITE , __sspcr1_bits );
__IO_REG32_BIT( SSPDR , 0xE0068008 , __READ_WRITE , __sspdr_bits );
__IO_REG32_BIT( SSPSR , 0xE006800C , __READ , __sspsr_bits );
__IO_REG32_BIT( SSPCPSR , 0xE0068010 , __READ_WRITE , __sspcpsr_bits );
__IO_REG32_BIT( SSPIMSC , 0xE0068014 , __READ_WRITE , __sspimsc_bits );
__IO_REG32_BIT( SSPRIS , 0xE0068018 , __READ_WRITE , __sspris_bits );
__IO_REG32_BIT( SSPMIS , 0xE006801C , __READ_WRITE , __sspmis_bits );
__IO_REG32_BIT( SSPICR , 0xE0068020 , __READ_WRITE , __sspicr_bits );
/***************************************************************************
**
** TIMER0
**
***************************************************************************/
__IO_REG32_BIT( T0IR , 0xE0004000 , __READ_WRITE , __ir_bits );
__IO_REG32_BIT( T0TCR , 0xE0004004 , __READ_WRITE , __tcr_bits );
__IO_REG32( T0TC , 0xE0004008 , __READ_WRITE );
__IO_REG32( T0PR , 0xE000400C , __READ_WRITE );
__IO_REG32( T0PC , 0xE0004010 , __READ_WRITE );
__IO_REG32_BIT( T0MCR , 0xE0004014 , __READ_WRITE , __mcr_bits );
__IO_REG32( T0MR0 , 0xE0004018 , __READ_WRITE );
__IO_REG32( T0MR1 , 0xE000401C , __READ_WRITE );
__IO_REG32( T0MR2 , 0xE0004020 , __READ_WRITE );
__IO_REG32( T0MR3 , 0xE0004024 , __READ_WRITE );
__IO_REG32_BIT( T0CCR , 0xE0004028 , __READ_WRITE , __ccr_bits );
__IO_REG32( T0CR0 , 0xE000402C , __READ );
__IO_REG32( T0CR1 , 0xE0004030 , __READ );
__IO_REG32( T0CR2 , 0xE0004034 , __READ );
__IO_REG32( T0CR3 , 0xE0004038 , __READ );
__IO_REG32_BIT( T0EMR , 0xE000403C , __READ_WRITE , __emr_bits );
/***************************************************************************
**
** TIMER1
**
***************************************************************************/
__IO_REG32_BIT( T1IR , 0xE0008000 , __READ_WRITE , __ir_bits );
__IO_REG32_BIT( T1TCR , 0xE0008004 , __READ_WRITE , __tcr_bits );
__IO_REG32( T1TC , 0xE0008008 , __READ_WRITE );
__IO_REG32( T1PR , 0xE000800C , __READ_WRITE );
__IO_REG32( T1PC , 0xE0008010 , __READ_WRITE );
__IO_REG32_BIT( T1MCR , 0xE0008014 , __READ_WRITE , __mcr_bits );
__IO_REG32( T1MR0 , 0xE0008018 , __READ_WRITE );
__IO_REG32( T1MR1 , 0xE000801C , __READ_WRITE );
__IO_REG32( T1MR2 , 0xE0008020 , __READ_WRITE );
__IO_REG32( T1MR3 , 0xE0008024 , __READ_WRITE );
__IO_REG32_BIT( T1CCR , 0xE0008028 , __READ_WRITE , __ccr_bits );
__IO_REG32( T1CR0 , 0xE000802C , __READ );
__IO_REG32( T1CR1 , 0xE0008030 , __READ );
__IO_REG32( T1CR2 , 0xE0008034 , __READ );
__IO_REG32( T1CR3 , 0xE0008038 , __READ );
__IO_REG32_BIT( T1EMR , 0xE000803C , __READ_WRITE , __emr_bits );
/***************************************************************************
**
** PWM
**
***************************************************************************/
__IO_REG32_BIT( PWMIR , 0xE0014000 , __READ_WRITE , __pwmir_bits );
__IO_REG32_BIT( PWMTCR , 0xE0014004 , __READ_WRITE , __pwmtcr_bits );
__IO_REG32( PWMTC , 0xE0014008 , __READ_WRITE );
__IO_REG32( PWMPR , 0xE001400C , __READ_WRITE );
__IO_REG32( PWMPC , 0xE0014010 , __READ_WRITE );
__IO_REG32_BIT( PWMMCR , 0xE0014014 , __READ_WRITE , __pwmmcr_bits );
__IO_REG32( PWMMR0 , 0xE0014018 , __READ_WRITE );
__IO_REG32( PWMMR1 , 0xE001401C , __READ_WRITE );
__IO_REG32( PWMMR2 , 0xE0014020 , __READ_WRITE );
__IO_REG32( PWMMR3 , 0xE0014024 , __READ_WRITE );
__IO_REG32( PWMMR4 , 0xE0014040 , __READ_WRITE );
__IO_REG32( PWMMR5 , 0xE0014044 , __READ_WRITE );
__IO_REG32( PWMMR6 , 0xE0014048 , __READ_WRITE );
__IO_REG32_BIT( PWMPCR , 0xE001404C , __READ_WRITE , __pwmpcr_bits );
__IO_REG32_BIT( PWMLER , 0xE0014050 , __READ_WRITE , __pwmler_bits );
/***************************************************************************
**
** A/D Converters
**
***************************************************************************/
__IO_REG32_BIT( AD0CR , 0xE0034000 , __READ_WRITE , __adcr_bits );
__IO_REG32_BIT( AD0DR , 0xE0034004 , __READ_WRITE , __addr_bits );
__IO_REG32_BIT( ADGSR , 0xE0034008 , __WRITE , __adgsr_bits );
__IO_REG32_BIT( AD1CR , 0xE0060000 , __READ_WRITE , __adcr_bits );
__IO_REG32_BIT( AD1DR , 0xE0060004 , __READ_WRITE , __addr_bits );
/***************************************************************************
**
** D/A Converter
**
***************************************************************************/
__IO_REG32_BIT( DACR , 0xE006C000 , __READ_WRITE , __dacr_bits );
/***************************************************************************
**
** RTC
**
***************************************************************************/
__IO_REG32_BIT( ILR , 0xE0024000 , __READ_WRITE , __ilr_bits );
__IO_REG32_BIT( CTC , 0xE0024004 , __READ , __ctc_bits );
__IO_REG32_BIT( CCR , 0xE0024008 , __READ_WRITE , __rtcccr_bits );
__IO_REG32_BIT( CIIR , 0xE002400C , __READ_WRITE , __ciir_bits );
__IO_REG32_BIT( AMR , 0xE0024010 , __READ_WRITE , __amr_bits );
__IO_REG32_BIT( CTIME0 , 0xE0024014 , __READ , __ctime0_bits );
__IO_REG32_BIT( CTIME1 , 0xE0024018 , __READ , __ctime1_bits );
__IO_REG32_BIT( CTIME2 , 0xE002401C , __READ , __ctime2_bits );
__IO_REG32_BIT( SEC , 0xE0024020 , __READ_WRITE , __sec_bits );
__IO_REG32_BIT( MIN , 0xE0024024 , __READ_WRITE , __min_bits );
__IO_REG32_BIT( HOUR , 0xE0024028 , __READ_WRITE , __hour_bits );
__IO_REG32_BIT( DOM , 0xE002402C , __READ_WRITE , __dom_bits );
__IO_REG32_BIT( DOW , 0xE0024030 , __READ_WRITE , __dow_bits );
__IO_REG32_BIT( DOY , 0xE0024034 , __READ_WRITE , __doy_bits );
__IO_REG32_BIT( MONTH , 0xE0024038 , __READ_WRITE , __month_bits );
__IO_REG32_BIT( YEAR , 0xE002403C , __READ_WRITE , __year_bits );
__IO_REG32_BIT( ALSEC , 0xE0024060 , __READ_WRITE , __sec_bits );
__IO_REG32_BIT( ALMIN , 0xE0024064 , __READ_WRITE , __min_bits );
__IO_REG32_BIT( ALHOUR , 0xE0024068 , __READ_WRITE , __hour_bits );
__IO_REG32_BIT( ALDOM , 0xE002406C , __READ_WRITE , __dom_bits );
__IO_REG32_BIT( ALDOW , 0xE0024070 , __READ_WRITE , __dow_bits );
__IO_REG32_BIT( ALDOY , 0xE0024074 , __READ_WRITE , __doy_bits );
__IO_REG32_BIT( ALMON , 0xE0024078 , __READ_WRITE , __month_bits );
__IO_REG32_BIT( ALYEAR , 0xE002407C , __READ_WRITE , __year_bits );
__IO_REG32_BIT( PREINT , 0xE0024080 , __READ_WRITE , __preint_bits );
__IO_REG32_BIT( PREFRAC , 0xE0024084 , __READ_WRITE , __prefrac_bits );
/***************************************************************************
**
** Watchdog
**
***************************************************************************/
__IO_REG32_BIT( WDMOD , 0xE0000000 , __READ_WRITE , __wdmod_bits );
__IO_REG32( WDTC , 0xE0000004 , __READ_WRITE );
__IO_REG32_BIT( WDFEED , 0xE0000008 , __WRITE , __wdfeed_bits );
__IO_REG32( WDTV , 0xE000000C , __READ );
/***************************************************************************
**
** USB
**
***************************************************************************/
__IO_REG32_BIT( USBINTS , 0xe01fc1c0 , __READ_WRITE , __usbints_bits );
__IO_REG32_BIT( DEVINTS , 0xe0090000 , __READ , __devints_bits );
__IO_REG32_BIT( DEVINTEN , 0xe0090004 , __READ_WRITE , __devints_bits );
__IO_REG32_BIT( DEVINTCLR , 0xe0090008 , __READ_WRITE , __devints_bits );
__IO_REG32_BIT( DEVINTSET , 0xe009000c , __READ_WRITE , __devints_bits );
__IO_REG8_BIT( DEVINTPRI , 0xe009002c , __WRITE , __devintpri_bits );
__IO_REG32_BIT( ENDPINTS , 0xe0090030 , __READ , __endpints_bits );
__IO_REG32_BIT( ENDPINTEN , 0xe0090034 , __READ_WRITE , __endpints_bits );
__IO_REG32_BIT( ENDPINTCLR , 0xe0090038 , __READ_WRITE , __endpints_bits );
__IO_REG32_BIT( ENDPINTSET , 0xe009003c , __READ_WRITE , __endpints_bits );
__IO_REG32_BIT( ENDPINTPRI , 0xe0090040 , __WRITE , __endpints_bits );
__IO_REG32_BIT( REALIZEENDP , 0xe0090044 , __READ_WRITE , __realizeendp_bits );
__IO_REG32_BIT( ENDPIND , 0xe0090048 , __WRITE , __endpind_bits );
__IO_REG32_BIT( MAXPACKSIZE , 0xe009004c , __READ_WRITE , __maxpacksize_bits );
__IO_REG32( RCVEDATA , 0xe0090018 , __READ );
__IO_REG32_BIT( RCVEPKTLEN , 0xe0090020 , __READ , __rcvepktlen_bits );
__IO_REG32( TDATA , 0xe009001c , __READ_WRITE );
__IO_REG32_BIT( TPKTLEN , 0xe0090024 , __WRITE , __transmitpktlen_bits );
__IO_REG32_BIT( USBCTRL , 0xe0090028 , __READ_WRITE , __usbctrl_bits );
__IO_REG32_BIT( CMDCODE , 0xe0090010 , __WRITE , __cmdcode_bits );
__IO_REG32_BIT( CMDDATA , 0xe0090014 , __READ , __cmddata_bits );
__IO_REG32_BIT( DCREV , 0xe009007c , __READ_WRITE , __dcrev_bits );
__IO_REG32_BIT( DMARQSTSTAT , 0xe0090050 , __READ , __dmarqstdiv_bits );
__IO_REG32_BIT( DMARQSTCLR , 0xe0090054 , __READ_WRITE , __dmarqstdiv_bits );
__IO_REG32_BIT( DMARQSTSET , 0xe0090058 , __READ_WRITE , __dmarqstdiv_bits );
__IO_REG32_BIT( UDCAHEAD , 0xe0090080 , __READ_WRITE , __udcahead_bits );
__IO_REG32_BIT( EPDMASTAT , 0xe0090084 , __READ , __epdmadiv_bits );
__IO_REG32_BIT( EPDMAEN , 0xe0090088 , __READ_WRITE , __epdmadiv_bits );
__IO_REG32_BIT( EPDMADIS , 0xe009008c , __READ_WRITE , __epdmadiv_bits );
__IO_REG32_BIT( DMAINTSTAT , 0xe0090090 , __READ , __dmaintstat_bits );
__IO_REG32_BIT( DMAINTEN , 0xe0090094 , __READ_WRITE , __dmaintstat_bits );
__IO_REG32_BIT( NEWDDRINTSTAT , 0xe00900ac , __READ , __newdddiv_bits );
__IO_REG32_BIT( NEWDDRINTCLR , 0xe00900b0 , __READ_WRITE , __newdddiv_bits );
__IO_REG32_BIT( NEWDDRINTSET , 0xe00900b4 , __READ_WRITE , __newdddiv_bits );
__IO_REG32_BIT( EOTINTSTAT , 0xe00900a0 , __READ , __newdddiv_bits );
__IO_REG32_BIT( EOTINTCLR , 0xe00900a4 , __READ_WRITE , __newdddiv_bits );
__IO_REG32_BIT( EOTINTSET , 0xe00900a8 , __READ_WRITE , __newdddiv_bits );
__IO_REG32_BIT( SYSERRINTSTAT , 0xe00900b8 , __READ , __newdddiv_bits );
__IO_REG32_BIT( SYSERRINTCLR , 0xe00900bc , __READ_WRITE , __newdddiv_bits );
__IO_REG32_BIT( SYSERRINTSET , 0xe00900c0 , __READ_WRITE , __newdddiv_bits );
__IO_REG32_BIT( MODULEID , 0xe00900fc , __READ , __moduleid_bits );
__IO_REG32_BIT( PLL48CON , 0xE01FC0A0 , __READ_WRITE , __pllcon_bits );
__IO_REG32_BIT( PLL48CFG , 0xE01FC0A4 , __READ_WRITE , __pllcfg_bits );
__IO_REG32_BIT( PLL48STAT , 0xE01FC0A8 , __READ , __pllstat_bits );
__IO_REG32_BIT( PLL48FEED , 0xE01FC0AC , __WRITE , __pllfeed_bits );
/***************************************************************************
** Assembler-specific declarations
***************************************************************************/
#ifdef __IAR_SYSTEMS_ASM__
#endif /* __IAR_SYSTEMS_ASM__ */
/***************************************************************************
**
** Interrupt vector table
**
***************************************************************************/
#define RESETV 0x00 /* Reset */
#define UNDEFV 0x04 /* Undefined instruction */
#define SWIV 0x08 /* Software interrupt */
#define PABORTV 0x0c /* Prefetch abort */
#define DABORTV 0x10 /* Data abort */
#define IRQV 0x18 /* Normal interrupt */
#define FIQV 0x1c /* Fast interrupt */
/***************************************************************************
**
** VIC Interrupt channels
**
***************************************************************************/
#define VIC_WDT 0 /* Watchdog */
#define VIC_SW 1 /* Software interrupts */
#define VIC_DEBUGRX 2 /* Embedded ICE, DbgCommRx */
#define VIC_DEBUGTX 3 /* Embedded ICE, DbgCommTx */
#define VIC_TIMER0 4 /* Timer 0 (Match 0-3 Capture 0-3) */
#define VIC_TIMER1 5 /* Timer 1 (Match 0-3 Capture 0-3) */
#define VIC_UART0 6 /* UART 0 (RLS, THRE, RDA, CTI) */
#define VIC_UART1 7 /* UART 1 (RLS, THRE, RDA, CTI, MSI) */
#define VIC_PWM0 8 /* PWM 0 (Match 0-6 Capture 0-3) */
#define VIC_I2C 9 /* I2C 0 (SI) */
#define VIC_SPI 10 /* SPI 0 (SPIF, MODF) */
#define VIC_SSP 11 /* SSP */
#define VIC_PLL 12 /* PLL lock (PLOCK) */
#define VIC_RTC 13 /* RTC (RTCCIF, RTCALF) */
#define VIC_EINT0 14 /* External interrupt 0 (EINT0) */
#define VIC_EINT1 15 /* External interrupt 1 (EINT1) */
#define VIC_EINT2 16 /* External interrupt 2 (EINT2) */
#define VIC_EINT3 17 /* External interrupt 3 (EINT3) */
#define VIC_AD0 18 /* A/D converter 0 */
#define VIC_I2C1 19 /* I2C 1 */
#define VIC_BOD 20 /* Brown out detect */
#define VIC_AD1 21 /* A/D converter 1 */
#define VIC_USB 22 /* USB Low and High priority */
#endif /* __IOLPC2148_H */
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