maxplusii_to_quartus_name_mapping.txt

基于fpga和sopc的用VHDL语言编写的EDA的VGA图像显示控制器

 -- Copyright (C) 1991-2004 Altera Corporation
 -- Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 -- support information,  device programming or simulation file,  and any other
 -- associated  documentation or information  provided by  Altera  or a partner
 -- under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 -- to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 -- other  use  of such  megafunction  design,  netlist,  support  information,
 -- device programming or simulation file,  or any other  related documentation
 -- or information  is prohibited  for  any  other purpose,  including, but not
 -- limited to  modification,  reverse engineering,  de-compiling, or use  with
 -- any other  silicon devices,  unless such use is  explicitly  licensed under
 -- a separate agreement with  Altera  or a megafunction partner.  Title to the
 -- intellectual property,  including patents,  copyrights,  trademarks,  trade
 -- secrets,  or maskworks,  embodied in any such megafunction design, netlist,
 -- support  information,  device programming or simulation file,  or any other
 -- related documentation or information provided by  Altera  or a megafunction
 -- partner, remains with Altera, the megafunction partner, or their respective
 -- licensors. No other licenses, including any licenses needed under any third
 -- party's intellectual property, are provided herein.

 -- VERSION "Version 4.1 Build 181 06/29/2004 SJ Full Version"
 -- DATE "09/12/2004 09:47:03"

Conversion results for vgarom
+-----------------------+----------------------+
| MAX+PLUS II node name | Quartus II node name |
+-----------------------+----------------------+
| |A18                  | A[18]                |
| |addr0                | addr[0]              |
| |addr1                | addr[1]              |
| |addr2                | addr[2]              |
| |addr3                | addr[3]              |
| |addr4                | addr[4]              |
| |addr5                | addr[5]              |
| |addr6                | addr[6]              |
| |addr7                | addr[7]              |
| |addr8                | addr[8]              |
| |addr9                | addr[9]              |
| |addr10               | addr[10]             |
| |addr11               | addr[11]             |
| |addr12               | addr[12]             |
| |addr13               | addr[13]             |
| |addr14               | addr[14]             |
| |addr15               | addr[15]             |
| |addr16               | addr[16]             |
| |addr17               | addr[17]             |
| |CLK1                 | CLK[1]               |
| |data80               | data[80]             |
| |data81               | data[81]             |
| |data82               | data[82]             |
| |data83               | data[83]             |
| |data84               | data[84]             |
| |data85               | data[85]             |
| |data86               | data[86]             |
| |data87               | data[87]             |
| |OE1                  | OE[1]                |
+-----------------------+----------------------+